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Cypress
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| Part No. |
CY7C09359V 7C09359V
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| OCR Text |
... the lower byte (I/O0-I/O 8 for x18, I/O0-I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as ... |
| Description |
3.3V 4K/8K x 18Synchronous Dual-Port Static RAM
From old datasheet system
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| File Size |
347.71K /
17 Page |
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Cypress
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| Part No. |
CY7C09359 7C09359
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| OCR Text |
... the lower byte (I/O0-I/O 8 for x18, I/O0-I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as ... |
| Description |
4K/8K x 18Synchronous Dual-Port Static RAM
From old datasheet system
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| File Size |
333.11K /
18 Page |
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it Online |
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Cypress
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| Part No. |
CY7C09579V CY7C09569V 7C09579V
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| OCR Text |
...abilities on Right Port (x36 to x18 or x9) Byte-Select Capabilities on Left Port 100-MHz Pipelined Operation High-speed clock to data access 5/6/8 ns * 3.3V Low operating power -- Active = 250 mA (typical) -- Standby = 10 A (typical) * Full... |
| Description |
3.3V 16K/32K x 36FLEx36 Synchronous Dual-Port Static RAM
From old datasheet system
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| File Size |
500.11K /
28 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1354V25 CY7C1356V25 7C1354V
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| OCR Text |
...Pin Definitions (100-Pin TQFP)
x18 Pin Location 37, 36, 32-35, 44-50, 80-83, 99, 100 93, 94 x36 Pin Location 37, 36, 32-35, 44-50, 81-83, 99, 100 93, 94, 95, 96 Name A0 A1 A BWSa BWSb BWSc BWSd WE I/O Type InputSynchronous InputSynchronous... |
| Description |
256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture
From old datasheet system
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| File Size |
339.06K /
26 Page |
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it Online |
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Sony
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| Part No. |
CXK77B1840AGB CXK77B3640AGB
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| OCR Text |
...defined as SA address inputs in x18 LW SRAMs. 2. Pad Location 6B is a true no-connect. However, it is defined as an SA address input in 8Mb and 16Mb LW SRAMs. 3. Pad Location 2B is a true no-connect. However, it is defined as an SA address ... |
| Description |
4Mb Late Write HSTL High Speed Synchronous SRAMs (128K x 36 or 256K x 18 Organization)
From old datasheet system
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| File Size |
283.45K /
33 Page |
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IDT
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| Part No. |
IDT72V7250 IDT72V7240 IDT72V72100 IDT72V7230 IDT72V7290
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| OCR Text |
...- x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out Big-Endian/Little-Endian user selectable word representation Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consu... |
| Description |
3.3 VOLT HIGH-DENSITY SUPERSYNC II? 72-BIT FIFO
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| File Size |
423.44K /
42 Page |
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it Online |
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Samsung Electronic
SAMSUNG [Samsung semiconductor]
SAMSUNG[Samsung semiconductor]
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| Part No. |
K4R881869 K4R881869M K4R881869M-NCK8 K4R881869M-NBCCG6 K4R881869M-NCK7
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| OCR Text |
...r management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage/bandwidth or for error correction.
Preliminary Direct RDRAMTM
SAMSUNG 001 K4R88xx69A-Nxxx
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| Description |
288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
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| File Size |
4,078.30K /
64 Page |
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it Online |
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Price and Availability
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