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| Part No. |
K7D161888B-HC330 K7D161888B-HC250 K7D161888B-HC300
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| OCR Text |
... clock and data inputs are regi stered at the following rising edge of k clock. during ddr write operati ons, addresses and controls are registered at the first rising edge of k clock and data inputs are registered twic e at the following... |
| Description |
1M X 18 DDR SRAM, 0.2 ns, PBGA153
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| File Size |
377.60K /
16 Page |
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it Online |
Download Datasheet
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HYNIX SEMICONDUCTOR INC
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| Part No. |
DU5162ETR-FAC DU5162ETR-E3C H5DU5182ETR-E3C
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| OCR Text |
...ands are masked when cs is regi stered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an acti... |
| Description |
32M X 16 DDR DRAM, 0.65 ns, PDSO66
32M X 16 DDR DRAM, 0.75 ns, PDSO66
64M X 8 DDR DRAM, 0.75 ns, PDSO66
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| File Size |
377.16K /
30 Page |
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it Online |
Download Datasheet |
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HYNIX SEMICONDUCTOR INC
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| Part No. |
HY5DU121622DTP-D43I
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| OCR Text |
...ands are masked when cs is regi stered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an acti... |
| Description |
32M X 16 DDR DRAM, 0.7 ns, PDSO66
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| File Size |
220.88K /
29 Page |
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it Online |
Download Datasheet |
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INTEGRATED SILICON SOLUTION INC
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| Part No. |
IS61DDPB21M18A-550M3LI
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| OCR Text |
...s inputs: these inputs are regi stered and must meet the setup and hold times around the rising edge of k. these inputs are ignored when device is deselected. dq0 - dqn bidir data input and output signals. i nput data must meet setup a... |
| Description |
1M X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
547.82K /
30 Page |
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it Online |
Download Datasheet |
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Price and Availability
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