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				ANALOG DEVICES INC Analog Devices, Inc.
Part No.	ADSP-2189NBSTZ-320 ANALOGDEVICESINC-ADSP-2184NKSTZ-320 ADSP-2188NKCAZ-320 ADSP-2189NBCAZ-3202 ADSP-2189NBSTZ-3202
OCR Text	...cycle. the adsp-218xns flexible arch itecture and comprehensive instruction set allow the proce ssor to perform multiple opera- tions in parallel. in one proc essor cycle, adsp-218xn series members can: ? generate the next program address...
Description	DSP Microcomputer 24-BIT, 40 MHz, OTHER DSP, PBGA144 16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 192KB RAM; Package: 100 ld LQFP; No of Pins: 100; Temperature Range: Ind 24-BIT, 40 MHz, OTHER DSP, PQFP100
File Size	1,400.59K / 48 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY39100V388B-83MGC CY39100V208B-125NTXC CY39050V208-125NTC
OCR Text	... interface within the delta39k arch itecture. the lbc is exactly the same for every member of the delta39k cpld family. logic block cluster (lbc) the delta39k architecture consists of several logic block clusters, each of which have eig...
Description	Delta39K ISR CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA388 Delta39K ISR CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PQFP208 CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PQFP208
File Size	1,758.79K / 86 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY14E064L-SZ35XIT
OCR Text	... recall operation). this unique arch itecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14e064l supports unlimited reads and writes s...
Description
File Size	2,409.75K / 17 Page	View it Online	Download Datasheet

				Alliance Semiconductor, Corp.
Part No.	AS29F200T-55SC AS29F200T-55SI AS29F200T-55TC AS29F200B-90TC
OCR Text	...r transitions. control register arch i tecture permits alteration of memory contents only after successful completion of specific command sequences. during power up, the devi ce is set to read mode with all program/erase commands disabled w...
Description	5V 256K x 8/128K x 8 CMOS FLASH EEPROM 128K X 16 FLASH 5V PROM, 55 ns, PDSO44 5V 256K x 8/128K x 8 CMOS FLASH EEPROM 128K X 16 FLASH 5V PROM, 55 ns, PDSO48 5V 256K x 8/128K x 8 CMOS FLASH EEPROM 128K X 16 FLASH 5V PROM, 90 ns, PDSO48
File Size	192.00K / 20 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1475BV25 CY7C1471BV25-133AXI CY7C1473BV25
OCR Text	...atures no bus latency? (nobl?) arch itecture eliminates dead cycles between write and read cycles supports up to 133 mhz bus operations with zero wait states data transfers on every clock pin compatible and functionally equivalent to zb...
Description	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL architecture
File Size	802.98K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp. CYPRESS SEMICONDUCTOR CORP
Part No.	CY14B104L-BA15XCT CY14B104L-BA15XI
OCR Text	...l operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b104l/cy14b104n supports infinite reads and writes s...
Description	4 Mbit (512K x 8/256K x 16) nvSRAM 512K X 8 NON-VOLATILE SRAM, 15 ns, PBGA48
File Size	501.55K / 23 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY14E256LA-SZ25XI CY14E256LA-SZ25XIT CY14E256LA-SZ45XI CY14E256LA-SZ45XIT
OCR Text	...l operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14e256la supports infinite reads and writes similar to...
Description	256-Kbit (32 K × 8) nvSRAM
File Size	689.86K / 19 Page	View it Online	Download Datasheet

				CYPRESS SEMICONDUCTOR CORP
Part No.	CY7C1463AV33-100AXC CY7C1463AV33-100AXI CY7C1463AV33-100BZC CY7C1463AV33-100BZI CY7C1463AV33-100BZXC CY7C1463AV33-100BZXI CY7C1461AV33 CY7C1461AV33-100BZI CY7C1461AV33-100AXI CY7C1461AV33-100BZC CY7C1461AV33-100AXC CY7C1461AV33-133AXC CY7C1463AV33-133AXC CY7C1465AV33-133BGI CY7C1465AV33-100BGXC CY7C1465AV33-100BGI CY7C1465AV33-133BGC CY7C1465AV33-100BGXI CY7C1465AV33-100BGC CY7C1461AV33-133BZI
OCR Text	...atures no bus latency? (nobl?) arch itecture eliminates dead cycles between write and read cycles supports up to 133 mhz bus operations with zero wait states ? data is transferred on every clock pin compatible and functionally equivalen...
Description	36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL architecture 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??architecture
File Size	628.90K / 32 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1463AV33 CY7C1461AV33 CY7C1461AV33-133AXC CY7C1463AV33-133AXC CY7C1465AV33
OCR Text	...atures no bus latency? (nobl?) arch itecture eliminates dead cycles between write and read cycles supports up to 133 mhz bus operations with zero wait states ? data is transferred on every clock pin compatible and functionally equivalent...
Description	36-Mbit (1 M x 36/2 M x 18/512 k x 72) Flow-Through SRAM with NoBL architecture
File Size	821.84K / 34 Page	View it Online	Download Datasheet

				Aplus Integrated Circuits Aplus Intergrated Circuits
Part No.	ASM2012CB
OCR Text	...ini mize power dissipation. its arch itecture is similar to risc, with two stages of instruction pipe line. it allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (w hich ...
Description	VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
File Size	424.30K / 7 Page	View it Online	Download Datasheet

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