| |
|
 |
Taiyo Yuden Co., Ltd.
Nihon Inter Electronics, Corp.
Vectron International, Inc.
Samsung Semiconductor Co., Ltd.
|
| Part No. |
EP1K50TC144-1DX EP1K50TI144-1DX EP1K50FC484-2F EP1K50TC144-2F EP1K50FI484-2F EP1K50TI144-2F EP1K50QI208-1F EP1K50QC208-1F EP1K50FC484-3F EP1K50TI144-1F EP1K50FC484-1F EP1K50TC144-1F EP1K50QI208-3F EP1K50QC208-3F EP1K50TI144-1X EP1K50TI144-2DX EP1K50FC484-1X EP1K50FC484-2DX EP1K50TC144-2DX EP1K50FI484-1X EP1K50TC144-1X EP1K50FI484-2DX EP1K50TC144-2P EP1K50FI256-1F EP1K50TI144-1P EP1K50QI208-2DX EP1K50TI144-2P EP1K50FI484-1DX EP1K50FC484-1DX EP1K50FC256-2DX EP1K50FI256-1DX EP1K50FI484-3F
|
| OCR Text |
...s (LPM), DesignWare components, verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQ... |
| Description |
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 5-SOT-23 T&R
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SC-70 T&R
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R
Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 5-SC-70 T&R
Field Programmable Gate Array (FPGA) 现场可编程门阵列（FPGA
Field Programmable Gate Array (FPGA) 现场可编程门阵列FPGA
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 6-SC-70 T&R 现场可编程门阵列（FPGA
Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 5-SOT-23 T&R
|
| File Size |
657.07K /
86 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Altera
|
| Part No. |
EPM7128E EPM7064 EPM7160E EPM7032 MAX7000
|
| OCR Text |
...of parameterized modules (LPM), verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support - Altera's Master Programmin... |
| Description |
MAX7000
|
| File Size |
1,072.55K /
85 Page |
View
it Online |
Download Datasheet |
| |
|
|
Altera Corporation
|
| Part No. |
EP1K50FC256
|
| OCR Text |
...s (LPM), DesignWare components, verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQ... |
| Description |
Programmable Logic Device Family
|
| File Size |
648.49K /
86 Page |
View
it Online |
Download Datasheet |
| |
|
|
Cypress
|
| Part No. |
CY3130 3130
|
| OCR Text |
verilog Development System for CPLDs
Features
* Sophisticated CPLD design and verification system based on VHDL and verilog * Warp3(R) is based on the Workview Office(R) (PC) design environment -- Advanced graphical user interface for Win... |
| Description |
Warp3 VHDL and verilog Development System for CPLDs
From old datasheet system
|
| File Size |
136.94K /
6 Page |
View
it Online |
Download Datasheet |
| |
|
|
Altera Corporation
|
| Part No. |
ACEX1 EP1K10 EP1K100 EP1K30 EP1K50
|
| OCR Text |
...s (LPM), DesignWare components, verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQ... |
| Description |
Programmable Logic Device Family
|
| File Size |
380.98K /
86 Page |
View
it Online |
Download Datasheet |
| |
|
|
Electronic Theatre Controls, Inc.
List of Unclassifed Manufacturers
|
| Part No. |
EP1K10 EP1K100 EP1K30 ACEX1 EP1K50 EP1K30TI144-2
|
| OCR Text |
...s (LPM), DesignWare components, verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQ... |
| Description |
Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
Programmable Logic Device Family
|
| File Size |
385.71K /
86 Page |
View
it Online |
Download Datasheet |
| |
|
|
Altera Corporation
|
| Part No. |
EP1K30FC256 ACEX1K07
|
| OCR Text |
...s (LPM), DesignWare components, verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic
Table 2. ACEX 1K Packa... |
| Description |
Programmable Logic Family
From old datasheet system
Field Programmable Gate Array (FPGA)
|
| File Size |
828.19K /
88 Page |
View
it Online |
Download Datasheet |
| |
|
|
Cypress
|
| Part No. |
CY3120J CY3120 3120
|
| OCR Text |
... (16V8, 20V8, 22V10) * VHDL and verilog timing model output for use with third-party simulators * * * * * Timing simulation provided with Active-HDLTM Sim Release 3.3 from Aldec (PC only) -- Graphical waveform simulator -- Entry and modific... |
| Description |
Warp2VHDL Compiler for CPLDs
From old datasheet system
|
| File Size |
121.82K /
6 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
