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LSI Corporation
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| Part No. |
L80223
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| OCR Text |
...t l/t length and type lsb least-signi?cant bit mib management information base mlt3 multi-level transmission (3 levels) ms millisecond msb most-signi?cant bit mv millivolt nlp normal link pulse nrzi non-return to zero inverted nrz non-retur... |
| Description |
10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太网物理层处理
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| File Size |
546.52K /
192 Page |
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it Online |
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LSI Corporation
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| Part No. |
CW400X
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| OCR Text |
...hroughout this manual: a level-signi?cant signal that is true or valid when the signal is low always has an overbar ( ) over its name. an edge-signi?cant signal that initiates actions on a high-to-low transition always has an overbar ( ) ... |
| Description |
32-Bit, High Performance,Microprocessor Core family(32高性能微处理核芯系列芯
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| File Size |
586.90K /
210 Page |
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it Online |
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MURATA POWER SOLUTIONS INC
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| Part No. |
7812SR-C
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| OCR Text |
...itching regulators provide many signi? cant improvements over their linear coun- terparts: lower quiescent current (3ma vs. 5 ma), higher input voltage (40v vs. 32v), and better output accuracy (2% vs. 5%). all these features combine to ma... |
| Description |
1-OUTPUT 4.8 W DC-DC REG PWR SUPPLY MODULE
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| File Size |
435.58K /
6 Page |
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it Online |
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Xicor
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| Part No. |
AN140
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| OCR Text |
... in addition these values vary signi?cantly with temperature. the bias current (i b ) is controlled by a feedback loop from the laser diodes monitor diode (refer to figure 3). the monitor photo-diode and feedback loop cannot "track" th... |
| Description |
1 Gb/s Fiber Optic Transmitter Design using Xicor Digitally Controlled Potentiometers (XDCPs)
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| File Size |
226.89K /
11 Page |
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it Online |
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NXP Semiconductors N.V.
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| Part No. |
SC16C852V SC16C852VIBS SC16C852VIET
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| OCR Text |
...ntrolling cpu. ad0 is the least signi?cant bit and is address a0 during the address cycle, and ad7 is the most signi?cant bit and is address a7 during the address cycle. ad1 b3 45 ad2 a2 46 ad3 b2 47 ad4 a1 48 ad5 b1 1 ad6 c3 2 ad7 c1 3 cd ... |
| Description |
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
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| File Size |
218.79K /
54 Page |
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it Online |
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NXP Semiconductors N.V.
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| Part No. |
SC16C850VIBS
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| OCR Text |
...ntrolling cpu. ad0 is the least signi?cant bit and is address a0 during the address cycle, and ad7 is the most signi?cant bit and is address a7 during the address cycle. ad1 30 ad2 31 ad3 32 ad4 1 ad5 3 ad6 4 ad7 5 cd 26 i carrier detect (a... |
| Description |
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| File Size |
201.47K /
47 Page |
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it Online |
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