| |
|
 |
XILINX INC
|
| Part No. |
XC6SLX16-L1CSG324C XC6SLX150T-4FG676I
|
| OCR Text |
...egister 6-input l ook-up table (lut) logic and a rich selection of built-in system-level bloc ks. these include 18 kb (2 x 9 kb) block rams, second generation dsp4 8a1 slices, sdram memory controllers, enhanced mixed-mode clock management b... |
| Description |
FPGA, PBGA324
FPGA, PBGA676
|
| File Size |
250.95K /
10 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
ATMEL CORP
|
| Part No. |
AT40KEL040KW1SMV
|
| OCR Text |
...combined to produce one 4-input lut. this means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. there is a set/reset d flip-flop in every cell, the output of which may be tri-stated and fed back inter... |
| Description |
FPGA, 2304 CLBS, 40000 GATES, QFP160
|
| File Size |
459.86K /
40 Page |
View
it Online |
Download Datasheet |
| |
|
|
ATMEL CORP
|
| Part No. |
AT40KEL040KW1M-E
|
| OCR Text |
...combined to produce one 4-input lut. this means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. there is a set/reset d flip-flop in every cell, the output of which may be tri-stated and fed back inter... |
| Description |
FPGA, 2304 CLBS, 40000 GATES, QFP160
|
| File Size |
483.85K /
39 Page |
View
it Online |
Download Datasheet |
| |
|
|
INTEGRATED DEVICE TECHNOLOGY INC
|
| Part No. |
M2006-02I672.1600 M2006-02I627.3296LF
|
| OCR Text |
...iv mfec div mfec / rfec divider lut mfin divider lut fin_sel1:0 ref_sel dif_ref0 ndif_ref0 dif_ref1 ndif_ref1 p0_sel p1_sel vcso 0 1 m2006-02 fout0 nfout0 fout1 nfout1 fec_sel3:0 4 2 p0 div (1 or 4) mfin div (1, 4, 8, or 32) p1 div (1 or 4)... |
| Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
|
| File Size |
256.66K /
8 Page |
View
it Online |
Download Datasheet |
| |
|
|
Philips
|
| Part No. |
SAA7108E SAA7109E
|
| OCR Text |
... conditions Input formatter RGB lut Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) En... |
| Description |
PC-CODEC
|
| File Size |
741.22K /
204 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
