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AD[Analog Devices]
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| Part No. |
ADSP-21267SKSTZ-X ADSP-21267SKBCZ-X ADSP-21267
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| OCR Text |
...n set as other SHARC DSPs Super harvard Architecture--three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O 1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and 0.5M Bit in block 1) for simul... |
| Description |
Preliminary Technical Data
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| File Size |
472.72K /
44 Page |
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it Online |
Download Datasheet
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Motorola
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| Part No. |
F801FA60
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| OCR Text |
...rid controller engine with dual harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bit... |
| Description |
Search --To DSP56F801FA60
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| File Size |
662.29K /
44 Page |
View
it Online |
Download Datasheet
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Price and Availability
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