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Altera Corp
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| Part No. |
EPF6016
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| OCR Text |
... Register-rich, look-up table- (lut-) based architecture - OptiFLEX(R) architecture that increases device area efficiency - Typical gates ranging from 5,000 to 24,000 gates (see Table 1) - Built-in low-skew clock distribution tree - 100% fu... |
| Description |
IC,FPGA,1320-CELL,CMOS,BGA,100PIN,PLASTIC
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| File Size |
351.60K /
52 Page |
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it Online |
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Altera
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| Part No. |
EP1K30TC144-3 EP1K50QC20 EP1K10TC10 EP1K50QC208-1 EP1K100QC208-1 EP1K10TC100-3 EP1K50FC256-2 EP1K30
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| OCR Text |
...ure by combining look-up table (lut) architecture with EABs. lut-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM... |
| Description |
Programmable Logic Device Family
Acex 1K Device Family (2.5V)
IC,FPGA,72-CELL,CMOS,QFP,144PIN,PLASTIC
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| File Size |
515.52K /
86 Page |
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ALTERA
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| Part No. |
EPF6016TC1 EPF6016TC144-3 EPF6016ATC144-2 EPF6016ATC100-3
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| OCR Text |
... Register-rich, look-up table- (lut-) based architecture - OptiFLEX(R) architecture that increases device area efficiency - Typical gates ranging from 5,000 to 24,000 gates (see Table 1) - Built-in low-skew clock distribution tree - 100% fu... |
| Description |
Programmable Logic Device Family
Flex 6000 Device Family (5.0V)
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| File Size |
325.40K /
52 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2026
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| OCR Text |
...:0
2 2 3
M / R Divider
lut
Mfin Divider
lut
P Divider
lut
Figure 2: Simplified Block Diagram
M2025/26 Datasheet Rev 1.0
M2025/26 VCSO Based Clock PLL with AutoSwitch
Revised 30Jul2004
Integrated Circuit Sys... |
| Description |
SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
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| File Size |
333.73K /
12 Page |
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it Online |
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AVERLOGIC
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| Part No. |
AL260
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| OCR Text |
...tems Sharpness Control Built-in lut for Gamma Correction and Color Adjustment Dithering Logic for Color Depth Enhancement
Output Interface:
! ! Output resolution up to 1280x1024 @60Hz Analog Non-interlaced RGB/YPbPr and Digital RGB 24bi... |
| Description |
VIDEO ENHANCEMENT PROCESSOR
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| File Size |
329.25K /
4 Page |
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it Online |
Download Datasheet |
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Price and Availability
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