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				SpectraLinear Inc
Part No.	CY28317ZC-2 CY28317ZC-2T CY28317PVC-2 CY28317-2 CY28317PVC-2T
OCR Text	...t that controls the FS0:4 to be latched and enables all outputs. CY28316 will sample the FS0:4 inputs and enable all clock outputs after all the VDD become valid and VTT_PWRGD# is held LOW. 24_48MHz/ FS1 REF1/FS2 26 I/O 2 I/O...
Description	FTG for Mobile VIA⑩ PL133T and PLE133T Chipsets
File Size	259.87K / 20 Page	View it Online	Download Datasheet

				SpectraLinear Inc
Part No.	CY28341OXC-2 CY28341OXC-2T CY28341OC-2 CY28341-2 CY28341OC-2T CY28341ZC-2 CY28341ZC-2T
OCR Text	...threshold voltage, FS0 state is latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) I If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At pow...
Description	Universal Clock Chip for VIA?P4M/KT/KM400 DDR Systems Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
File Size	224.87K / 18 Page	View it Online	Download Datasheet

				Melexis Microelectronic Systems
Part No.	MLX10410
OCR Text	...hen all 8 outputs are inactive (latched value is low) the circuit automatically switches to power down mode. Diagnostic mode: when the DATAI is low and the STROBE is high, a 50K pull up to VCC is switched on, on the corresponding output cha...
Description	8 Fold High Side Driver
File Size	88.73K / 7 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY28341OXC-2 CY28341OXC-2T CY28341OC-2 CY28341-205 CY28341OC-2T CY28341ZC-2 CY28341ZC-2T CY28341-2
OCR Text	...threshold voltage, FS0 state is latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) I If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At pow...
Description	200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 SSOP-56 Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems Universal Clock Chip for VIA?P4M/KT/KM400 DDR Systems
File Size	316.41K / 19 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1231F-100AC CY7C1231F05
OCR Text	...presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:B] can be used to conduct Byte Write operations. Write operations are qualified by the Write...
Description	2-Mbit (128K x 18) Flow-through SRAM with NoBL Architecture 2-Mbit (128K x 18) Flow-through SRAM with NoBL⑩ Architecture
File Size	205.12K / 12 Page	View it Online	Download Datasheet

				SST
Part No.	SST39LF802C
OCR Text	...s ? hardware reset pin (rst#) ? latched address and data ? security-id feature ? sst: 128 bits; user: 128 words ? fast read access time: ? 70 ns for sst39vf801c/802c ? 55 ns for sst39lf801c/802c ? fast erase and word-program: ? sector-erase...
Description	(SST39LF801C / SST39LF802C) 8 Mbit (x16) Multi-Purpose Flash Plus
File Size	439.14K / 38 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT74SSTUBF32865ABKG8 IDT74SSTUBF32865A
OCR Text	...IGH, the D0..D21 inputs will be latched only when at least one Chip 1.8V LVCMOS Select input is LOW during the rising edge of the clock. When LOW, the D0...D21 inputs will be latched and redriven on every rising edge of the clock. SSTL_18 D...
Description	28-BIT 1:2 REGISTERED BUFFER WITH PARITY
File Size	339.95K / 17 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT74SSTUBH32865ABKG8 IDT74SSTUBH32865A
OCR Text	...IGH, the D0..D21 inputs will be latched only when at least one Chip 1.8V LVCMOS Select input is LOW during the rising edge of the clock. When LOW, the D0...D21 inputs will be latched and redriven on every rising edge of the clock. SSTL_18 D...
Description	28-BIT 1:2 REGISTERED BUFFER FOR DDR2
File Size	336.42K / 17 Page	View it Online	Download Datasheet

				SpectraLinear Inc
Part No.	CY28412OXC CY28412OXCT CY28412OC CY28412 CY28412OCT
OCR Text	...U frequency selection. Input is latched upon assertion (LOW) of VTT_PWRGD#/PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency selection. I...
Description	Clock Generator for Intel? Grantsdale Chipset Clock Generator for Intel㈢ Grantsdale Chipset
File Size	202.00K / 16 Page	View it Online	Download Datasheet

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