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  ddr-i ii Datasheet PDF File

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    NCP51145 NCP51145-17 NCP51145PDR2G NCP51145MNTAG

ON Semiconductor
Part No. NCP51145 NCP51145-17 NCP51145PDR2G NCP51145MNTAG
OCR Text ddr 1.8 amp source / sink v tt termination regulator the ncp51145 is a linear regulator designed to supply a regulated v tt termination vo...i out = 0 a v os ?16 ? +16 mv load regulation i out = 1.8 a, pv cc = 1.8 v, v ref = 0.9 v reg ...
Description DDR 1.8 Amp Source Termination Regulator

File Size 76.21K  /  6 Page

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    Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
Part No. ASM4SSTVF16857 ASM4SSTVF16857-48VT ASM4SSTVF16857-48TR ASM4SSTVF16857-48TT ASM4SSTVF16857-48VR
OCR Text DDR 14-Bit Registered Buffer ASM4SSTVF16857 LVCMOS level at a valid logic state since VREF may Features * Fully JEDEC JC40 - JC42....I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600,...
Description DDR 14-Bit Registered Buffer SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
Specialty Clock Management

File Size 147.94K  /  16 Page

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    Alliance Semiconductor Corp...
ALSC[Alliance Semiconductor Corporation]
Part No. ASM4SSTVF16859 ASM4SSTVF16859-64TT ASM4SSTVF16859-56QR ASM4SSTVF16859-56QT ASM4SSTVF16859-64TR
OCR Text DDR 13-Bit to 26-Bit Registered Buffer ASM4SSTVF16859 off. Note that RESETB should be supported with a Features Differential clo...I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600,...
Description DDR 13-Bit to 26-Bit Registered Buffer
Specialty Clock Management
CONNECTOR ACCESSORY

File Size 163.36K  /  16 Page

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    Alliance Semiconductor ...
ALSC[Alliance Semiconductor Corporation]
Part No. ASM4SSTVF32852 ASM4SSTVF32852-114BT ASM4ISSTVF32852-114BR ASM4ISSTVF32852-114BT ASM4SSTVF32852-114BR
OCR Text DDR 24-Bit to 48-Bit Registered Buffer ASM4SSTVF32852 Features Differential clock signals. Supports SSTL_2 class ii specifications ...I/O levels except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differenti...
Description    DDR 24-Bit to 48-Bit Registered Buffer
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114
Specialty Clock Management
2.3 V -2.7 V, DDR 24-bit to 48-bit registered buffer

File Size 106.12K  /  13 Page

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    HY5DU121622BLTP HY5DU12422 HY5DU121622BT-D43 HY5DU12422BT-D43 HY5DU12822BT-D4 HY5DU12822BT-D43

Hynix Semiconductor
ETC
Part No. HY5DU121622BLTP HY5DU12422 HY5DU121622BT-D43 HY5DU12422BT-D43 HY5DU12822BT-D4 HY5DU12822BT-D43
OCR Text DDR SDRAM HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP This document is a general product description and is subject to change wi...I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered D...
Description DDR SDRAM - 512Mb
HY5DU12422BTP

File Size 389.87K  /  37 Page

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    Cypress Semiconductor, Corp.
Part No. CY7C1550KV18-450BZC CY7C1550KV18-400BZC CY7C1548KV18-400BZC
OCR Text ddr ii+ sram 2-word burst architecture (2.0 cycle read latency) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-15879 rev. *i revised january 25, 2011 72-mbit ddr ii+ s...
Description Sync SRAM; Architecture: ddr-iI CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR ii SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 657.16K  /  31 Page

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    Altera, Corp.
Part No. EP1C6T256I6ES EP1C6T256I8ES EP1C6F256I6ES EP1C6T240C8ES EP1C6T100C6ES EP1C6T324I8ES EP1C6T144C8ES EP1C6T240I8ES EP1C6T256C8ES EP1C6Q324C7ES EP1C6T144C7ES EP1C4T100C8ES EP1C6F144C6ES
OCR Text ... a dedicated double data rate (ddr) interface to meet ddr sdram and fast cycle ram (fcram) memory requirements, cyclone devices are a c...i/o standards, including lvds at data rates up to 640 megabits per second (mbps), and 66- and 33-m...
Description Cyclone FPGA Family Data Sheet 气旋的FPGA系列数据手册

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    HY5DU56822BT-D43 HY5DU56822BT-D4_D43 HY5DU56422BT-D4_D43 HY5DU56422BT-D4 HY5DU56822BT-D HY5DU56822BT-D4/D43 HY5DU56422BT

Hynix Semiconductor
http://
Part No. HY5DU56822BT-D43 HY5DU56822BT-D4_D43 HY5DU56422BT-D4_D43 HY5DU56422BT-D4 HY5DU56822BT-D HY5DU56822BT-D4/D43 HY5DU56422BT-D4/D43 HY5DU56422BT-H HY5DU56422BT-M HY5DU56422BT-K
OCR Text DDR SDRAM HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 This document is a general product description and is subject to change without notice...I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered D...
Description DDR SDRAM - 256Mb
256M-P DDR SDRAM
IC,SDRAM,DDR,4X8MX8,CMOS,TSSOP,66PIN,PLASTIC

File Size 214.36K  /  32 Page

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    NCP51145MNTAG NCP51145PDR2G

ON Semiconductor
Part No. NCP51145MNTAG NCP51145PDR2G
OCR Text ddr 1.8 amp source / sink v tt termination regulator the ncp51145 is a linear regulator designed to supply a regulated v tt termination vo...i out = 0 a v os ?16 ? +16 mv load regulation i out = 1.8 a, pv cc = 1.8 v, v ref = 0.9 v reg ...
Description DDR 1.8 Amp Source / Sink Termination Regulator

File Size 76.90K  /  6 Page

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    Alliance Semiconductor ...
Part No. AS4C32M16D1A AS4C32M16D1A-5TCN AS4C32M16D1A-5TIN AS4C32M16D1A-CI
OCR Text ... mar. /201 5 32 m x 16 bit ddr synchronous dram (sdram) adv a nced ( rev. 1 .0 , mar . / 20 1 5 ) features ? ...i/o interface ? package: 66 pin tsop ii, 0.65mm pin pitch - p b and halogen free ...
Description 32M x 16 bit DDR Synchronous DRAM
Internal pipeline architecture

File Size 1,477.62K  /  64 Page

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