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Zarlink
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| Part No. |
ZL50110ZL50111ZL50114
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| OCR Text |
... a TDM backplane Dual reference Stratum 3, 4 and 4E PLL for synchronous operation TDM-to-TDM loopback of TDM streams
Packet Processing Functions * * * * * * Flexible, multi-protocol packet encapsulation Packet sequencing to allow lost pa... |
| Description |
1024 Channel (32 T1/E1) Circuit Emulation Services over Packet Processor
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| File Size |
1,358.81K /
107 Page |
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it Online |
Download Datasheet
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Zarlink Semiconductor
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| Part No. |
ZL50111
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| OCR Text |
... a TDM backplane Dual reference Stratum 3, 4 and 4E PLL for synchronous operation TDM-to-TDM loopback of TDM streams
Packet Processing Functions * * * * * * Flexible, multi-protocol packet encapsulation Packet sequencing to allow lost pa... |
| Description |
Telecomm/Datacomm, Other - Datasheet Reference
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| File Size |
1,394.88K /
107 Page |
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it Online |
Download Datasheet |
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ICS
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M1020 M1021 M1021-13-161.1328LF M1021-13I161.1328LF M1020-11-155.5200LF M1020-11I167.3280LF
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| OCR Text |
...can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1020/21 module includes a proprietary...4 5 6 7 8 9
PLL Ratio
(Pin Selectable)
(M1020) (M1021)
Output Clock (MHz)
(Pin Selectable)
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| Description |
Frequency Translation PLL Family with Loss of Lock indicator and Hitless Switching options
ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 9 X 9 MM, CERAMIC, LCC-36
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| File Size |
307.50K /
10 Page |
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Zarlink
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| Part No. |
MT9041B
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| OCR Text |
Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C3, C4, C8 and C16 outp... |
| Description |
T1/E1 System Synchronizer
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| File Size |
512.83K /
21 Page |
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it Online |
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ICS
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| Part No. |
MK2049-34A MK2049-34SAILF
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| OCR Text |
...ents, and Jitter Generation for Stratum 3, 4, and 4E Timing frequencies, or 10 to 36 MHz
* Accepts multiple inputs: 8 kHz backplane clock, Loop * Locks to 8 kHz + 100 ppm (External mode) * Buffer Mode allows jitter attenuation of 10 to 3... |
| Description |
77.76 MHz, OTHER CLOCK GENERATOR, PDSO20
3.3 Volt Communications Clock VCXO PLL
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| File Size |
84.11K /
8 Page |
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it Online |
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ICS
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| Part No. |
MK2049-36
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| OCR Text |
...ents, and Jitter Generation for Stratum 3, 4, and 4E
* Accepts multiple inputs: 8 kHz backplane clock or 10
to 50 MHz
* Locks to 8 kHz + 100 ppm (External mode) * Buffer Mode allows jitter attenuation of 10 - 50 MHz
input and x1/x0.... |
| Description |
3.3 Volt Communications Clock PLL
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| File Size |
76.13K /
7 Page |
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it Online |
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Price and Availability
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