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Cypress Semiconductor, Corp.
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| Part No. |
CY23S08SXI-2T CY23S08SXC-2T CY23S08SXI-4 CY23S08SXI-4T CY23S08SXC-4
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| OCR Text |
...um frequency timing generation (ssftg) technology. cypress is one of the pioneers of ssftg development, and designed this product so as not to filter off the spread spectrum feature of the reference i nput, assuming it exists. when a zero ... |
| Description |
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 140 MHz; Outputs: 8; Operating Range: -40 to 85 C 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 140 MHz; Outputs: 8; Operating Range: 0 to 70 C 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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| File Size |
204.64K /
11 Page |
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Cypress Semiconductor Corp.
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| Part No. |
W152
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| OCR Text |
ssftg reference signals * Two banks of four outputs each * Configuration options to halve, double, or quadruple the reference frequency refer to Table 1 to determine the specific option which meets your multiplication needs * Outputs may be... |
| Description |
Spread Aware Eight Output Zero Delay Buffer( 八输出零延迟缓冲
From old datasheet system
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| File Size |
144.71K /
7 Page |
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Cypress Semiconductor Corp.
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| Part No. |
W532
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| OCR Text |
...mance. Frequency Selection With ssftg In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating wavef... |
| Description |
Frequency Multiplying, Peak Reducing EMI Solution(频率倍增, 峰值减小EMI解决方案)
Clocks and Buffers
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| File Size |
113.54K /
8 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY2510ZC-1T CY2509ZC-1T
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| OCR Text |
...ad aware??designed to work with ssftg reference signals ? well suited to both 100- and 133-mhz designs ? ten (cy2509) or eleven (cy2510) lvcmos/lvttl outputs ? 50 ps typical peak cycle-to-cycle jitter ? single output enable pin for cy251... |
| Description |
2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 4.40 MM, TSSOP-24
2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 4.40 MM, TSSOP-24
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| File Size |
155.87K /
6 Page |
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CYPRESS[Cypress Semiconductor]
Cypress Semiconductor Corp.
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| Part No. |
CY2510ZC-1 CY2509ZC-1 CY2510 CY2509
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| OCR Text |
ssftg reference signals * Well suited to both 100- and 133-MHz designs * Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL outputs * Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the ou... |
| Description |
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer
Spread Aware, Ten/Eleven Output Zero Delay Buffer
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| File Size |
99.90K /
6 Page |
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it Online |
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Price and Availability
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