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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857CPAI IDTCSPT857CPFI
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| OCR Text |
...z ? very low skew: ? <100ps for pc1600 - pc2700 ? <75ps for pc3200 ? very low jitter: ? <75ps for pc1600 - pc2700 ? <50ps for pc3200 ? 2.5v av dd and 2.5v v ddq for pc1600-pc2700 ? 2.6v av dd and 2.6v v ddq for pc3200 ? cmos control sig... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
140.09K /
15 Page |
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Pericom Technology
PERICOM[Pericom Semiconductor Corporation]
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| Part No. |
PI6CVF857 PI6CVF857A PI6CVF857AE PI6CVF857NF PI6CVF857ZDE
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| OCR Text |
...ck input * Operates at 2.5V for PC1600, PC2100, PC2700, and 2.6V for PC3200 * Packaging (Pb-free & Green available, select packages): - 48-pin TSSOP - 40-pin TQFN - 56-ball VFBGA
Product Description
PI6CVF857 PLL clock device is develop... |
| Description |
1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
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| File Size |
298.86K /
14 Page |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY2SSTV16857 CY2SSTV16857ZC CY2SSTV16857ZCT CY2SSTV16857ZI CY2SSTV16857ZIT CY2SSTV16857ZXC CY2SSTV16857ZXCT CY2SSTV16857ZXI CY2SSTV16857ZXIT
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| OCR Text |
... VOL Supply Voltage Description PC1600,2100,2700 PC3200 Condition Min. 2.5 2.5 1.25 VREF - 40 mV RESET RESET VDD/VDDQ = 2.3V to 2.7V, IOL = 100 A, VDD = 2.3 to 2.7V VDD/VDDQ = 2.3V, IOL = 16 mA, VDD = 2.3V 1.7 0.7 0.2 0.35 Typ. 2.6 2.6 1.3 ... |
| Description |
14-Bit Registered Buffer PC2700-/PC3200-Compliant
SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 0.240 INCH, MO-153, TSSOP2-48
14-Bit Registered Buffer PC2700-/PC3200-Compliant SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
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| File Size |
139.36K /
8 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
IDT74SSTVN16859NL
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| OCR Text |
...esigned for 2.3v-2.7v v dd for pc1600 - pc2700 and 2.5v-2.7v v dd for pc3200, and supports low standby operation. all data inputs and outputs are sstl_2 level compatible with jedec standard for sstl_2. reset is an lvcmos input since it m... |
| Description |
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
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| File Size |
72.61K /
7 Page |
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it Online |
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