| |
|
 |
Philips
|
| Part No. |
PNX1500
|
| OCR Text |
...ction word (VLIW) architecture. Five issue slots enable up to five simultaneous RISC-like operations to be scheduled into only one VLIW inst...level of programmability provides tremendous flexibility in handling custom datastreams, adapting to... |
| Description |
Processor Miscellaneous
|
| File Size |
115.31K /
8 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
ATMEL
|
| Part No. |
XMEGAD
|
| OCR Text |
... real time counter (rtc), up to five flexible 16-bit timer/counters with compare modes and pwm, up to four usarts, one i 2 c and smbus compa...level inte rrupt controller? on page 95 for more details on this. 3.3 architectural overview in ord... |
| Description |
Interrupts and Programmable Multi-level Interrupt Controller
|
| File Size |
3,595.57K /
309 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Cypress
|
| Part No. |
CY3120J CY3120 3120
|
| OCR Text |
...ection shows code segments from five sample design files. The top portion of each example features the entity declaration. Behavioral Descri...level entry methods, structural VHDL provides a method for designing at a very low level. In structu... |
| Description |
Warp2VHDL Compiler for CPLDs From old datasheet system
|
| File Size |
121.82K /
6 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
IDT
|
| Part No. |
IDT79R3052E IDT79R3052 IDT79R3051E IDT79R3051
|
| OCR Text |
...n rate. The CPU core contains a five stage pipeline and 32 orthogonal 32-bit registers. The IDT79R3051 family implements the MIPS ISA. In fa...level of performance. This performance is based on: * An efficient execution engine. The CPU perform... |
| Description |
RISControllers?
|
| File Size |
333.66K /
26 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|