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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1353-40AC CY7C1353-66AC
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| OCR Text |
...w, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a desel... |
| Description |
256Kx18 Flow-Through SRAM with NoBL Architecture 256K X 18 ZBT SRAM, 14 ns, PQFP100 256Kx18 Flow-Through SRAM with NoBL Architecture 256K X 18 ZBT SRAM, 11 ns, PQFP100
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| File Size |
162.65K /
13 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1339G-166BGC CY7C1339G-133AXE CY7C1339G-200BGXI CY7C1339G-200BGXC CY7C1339G-250BGXC
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| OCR Text |
...o pins. when low, the i/o pins behave as out puts. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. 234 567 1 a b c d e... |
| Description |
4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 3.5 ns, PBGA119 4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 4 ns, PQFP100 4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 2.8 ns, PBGA119 4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 2.6 ns, PBGA119
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| File Size |
382.78K /
18 Page |
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it Online |
Download Datasheet
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Cypress Semiconductor, Corp. CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1368C-200AJXI CY7C1368C-200AXC
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| OCR Text |
.../o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- syn... |
| Description |
9-Mbit (256K x 32) Pipelined DCD Sync SRAM 256K X 32 CACHE SRAM, 3 ns, PQFP100
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| File Size |
387.03K /
18 Page |
View
it Online |
Download Datasheet
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1347-100AI
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. 83 adv input- syn... |
| Description |
x36 Fast Synchronous SRAM x36快速同步SRAM
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| File Size |
312.69K /
15 Page |
View
it Online |
Download Datasheet
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1328G-133AXC
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| OCR Text |
.../o pins. when low, the i/o pins behave as outputs. when deasserted high, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- synch... |
| Description |
4-Mbit (256K x 18) Pipelined DCD Sync SRAM 256K X 18 CACHE SRAM, 4 ns, PQFP100
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| File Size |
350.38K /
16 Page |
View
it Online |
Download Datasheet
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