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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
CV183-2APAG
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| OCR Text |
...own spread and others ? support smbus block read/write, byte read/write ? available in tssop package functional block diagram key features ?...i/o 33.33mhz. src0, 2 differential clock output enable, control src0 and src2, 0 = enable. mode is... |
| Description |
96 MHz, PROC SPECiFiC CLOCK GENERATOR, PDSO64
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| File Size |
170.42K /
22 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
9214DGLF
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| OCR Text |
...oe pin being high, and 1 in its smbus output control register bit. the pll receives a reference clock, clk_int/c and outputs a clock signal ...i/o data p in of smbus circuitr y , 5v tolerant 11 oe in active high input for enabling outputs. ... |
| Description |
9214 SERiES, PLL BASED CLOCK DRiVER, 4 TRUE OUTPUT(S), 0 iNVERTED OUTPUT(S), PDSO28
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| File Size |
307.91K /
18 Page |
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it Online |
Download Datasheet
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