|
|
|
Skyworks Solutions
|
Part No. |
AAT4702IXS-1-T1
|
OCR Text |
...= v in 1 a i lim current limit rising edge; r set = open 100 150 200 ma rset_int current limit internal set resistor 50 k v uvlo under-voltage lockout threshold rising edge 1.8 2.4 v v uvlo_hys under-voltage lockout hysteresis 0.2 v ldo... |
Description |
Auto-Restarting Current Limiting Load Switch with LDO Regulator Active Low Enabled
|
File Size |
745.81K /
20 Page |
View
it Online |
Download Datasheet |
|
|
|
Alpha & Omega Semiconductor
|
Part No. |
AOZ1212DI
|
OCR Text |
...voltage lockout threshold v in rising v in falling 4.34.1 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 2v 23 ma i off shutdown supply current v en = 0v 32 0 a v fb feedback voltage 0.782 0.8 0.818 v load regulation... |
Description |
EZBuck DC-DC Buck Regulators Power ICs
|
File Size |
510.67K /
18 Page |
View
it Online |
Download Datasheet |
|
|
|
Alpha & Omega Semiconductor
|
Part No. |
AOZ1210AI
|
OCR Text |
...voltage lockout threshold v in rising v in falling 4.34.1 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 2v 23 ma i off shutdown supply current v en = 0v 32 0 a v fb feedback voltage 0.782 0.8 0.818 v load regulation... |
Description |
EZBuck DC-DC Buck Regulators Power ICs
|
File Size |
363.99K /
14 Page |
View
it Online |
Download Datasheet |
|
|
|
Alpha & Omega Semiconductor
|
Part No. |
AOZ1057AIL
|
OCR Text |
...voltage lockout threshold v in rising v in falling 4.003.70 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en >1.2v 23 ma i off shutdown supply current v en = 0v 11 0 a v fb feedback voltage 0.782 0.8 0.818 v load regulat... |
Description |
EZBuck DC-DC Buck Regulators Power ICs
|
File Size |
530.76K /
15 Page |
View
it Online |
Download Datasheet |
|
|
|
Data Delay Devices, Inc...
|
Part No. |
3D7523-10 3D7523-25 3D7523-50
|
OCR Text |
... samples the data input at the rising edge of the input clock. the sampled data is used in conjunction with the clock rising and falling edges to generate the by- phase level manchester code. the encoder employs the timing of the c... |
Description |
MONOLITHIC MANCHESTER ENCODER/DECODER
|
File Size |
154.18K /
5 Page |
View
it Online |
Download Datasheet |
|
|
|
Integrated Device Techn...
|
Part No. |
72255LA10PFG8 72255LA10PFGI8 72255LA10TFG8
|
OCR Text |
... written into the fifo on every rising edge of wclk when wen is asserted. the output port is controlled by a read clock (rclk) input and read enable ( ren ) input. data is read from the fifo on every rising edge of rclk when ren is asse... |
Description |
CMOS SuperSync FIFO
|
File Size |
480.40K /
27 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|