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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
ICS2059GI-02T
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| OCR Text |
...cy within a phase-locked loop (pll), the output clock is phase and frequency locked to the input clock. through selection of external loo...if unused, connect to ground. 14 iclk1 input input clock connection 1. connect an input reference cl... |
| Description |
27 MHz, VIDEO CLOCK GENERATOR, PDSO16
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| File Size |
314.51K /
12 Page |
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OKI SEMICONDUCTOR CO., LTD.
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| Part No. |
MSM7583GS-BK
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| OCR Text |
... output gain adjust
S E L
PLL
TXCI
1/10 ENV SG +1 VREF
To internal SG
LPF
D/A
To monitor output of each block TEST1, T...If TXW pin is "1", modulation data is output. (Refer to Fig. 1.) I+, I- Quadrature modulation signal... |
| Description |
pie/4 Shift QPSK MODEM 馅饼/ 4移调制调制解调器
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| File Size |
216.46K /
23 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
IDT5992A-2J IDT5992A-5JI IDT5992A-7JI
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| OCR Text |
PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM
FEATURES:
*...if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore,... |
| Description |
EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|LDCC|32PIN|PLASTIC 八分布式输出时钟驱动器| LDCC | 32脚|塑料
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| File Size |
117.42K /
8 Page |
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it Online |
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