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BX2639LT XA2016 X93256 MBRF2 100002 NC7SZ00 PT50M 2N3458
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  nsd Datasheet PDF File

For nsd Found Datasheets File :: 148    Search Time::1.344ms    
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    Philips
Part No. 74HC_HCT112 74HC112PW 74HCT112PW 74HC112N 74HC112D 74HC112DB 74HCT112N
OCR Text ...idual nJ, nK, clock (nCP), set (nsd) and reset (nRD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT112 The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless ...
Description 74HC112;74HCT112; dual JK flip-flop with set and reset; negative-edge trigger

File Size 87.18K  /  15 Page

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    adi
Part No. AD9736AD9735AD9734
OCR Text ... 50 MHz Noise Spectral Density (nsd) fDAC = 1200 MSPS, fOUT = 100 MHz fDAC = 1200 MSPS, fOUT = 316 MHz fDAC = 1200 MSPS, fOUT = 550 MHz Temp Test Level Min Typ 1200 TBD TBD TBD TBD 80 77 63 55 85 84 74 65 -165 -164 -158 -155 Max Min AD9735 ...
Description 14-Bit, 1.2 GSPS TxDAC+ D/A Converter

File Size 188.58K  /  8 Page

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    74LVC109 74LVC109D 74LVC109DB 74LVC109PW 74LVC109PWDH 74LVC109_3

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74LVC109 74LVC109D 74LVC109DB 74LVC109PW 74LVC109PWDH 74LVC109_3
OCR Text ...Propagation delay nCP to nQ, nQ nsd to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VI = GND to VCC1 CONDITIONS TYPICAL 4.0 4.5 4.5 250 5.0 27 UNIT ns MHz pF pF CL = 50 pF; VC...
Description From old datasheet system
Dual JK flip-flop with set and reset; positive-edge trigger

File Size 103.23K  /  10 Page

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    74HC74 74HC74D 74HC74N 74HCT74 74HCT74D 74HCT74DB 74HCT74N 74HCT74PW

Philips Semiconductors
Part No. 74HC74 74HC74D 74HC74N 74HCT74 74HCT74D 74HCT74DB 74HCT74N 74HCT74PW
OCR Text ...propagation delay nCP to nQ, nQ nsd to nQ, nQ nRD to nQ, nQ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequ...
Description Dual D-type flip-flop with set and reset positive-edge trigger
Dual D-type flip-flop with set and reset; positive-edge trigger

File Size 98.80K  /  13 Page

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    74LVC74ABQ 74LVC74ADB NXPSEMICONDUCTORS-74LVC74ABQ115

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NXP Semiconductors N.V.
Part No. 74LVC74ABQ 74LVC74ADB NXPSEMICONDUCTORS-74LVC74ABQ115
OCR Text ...nal description Table 3. Input nsd L H L [1] Function table[1] Output nRD H L L nCP X X X nD X X X nQ H L H nQ L H H H = HIGH voltage level L = LOW voltage level X = don't care Table 4. Input nsd H H [1] Function table[1] Out...
Description Dual D-type flip-flop with set and reset; positive-edge trigger 带设置和复位功能的双D触发器;上升沿触

File Size 95.91K  /  16 Page

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    PHILIPS[Philips Semiconductors]
Part No. 74ALVC74PW 74ALVC74 74ALVC74BQ 74ALVC74D
OCR Text ...00 tPHL/tPLH propagation delay nsd, nRD to nQ, nQ VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 fmax CI CPD Notes 1. CPD is used to determine the ...
Description Dual D-type flip-flop with set and reset; positive-edge trigger

File Size 97.62K  /  20 Page

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    CA316202 CA3162E CA3162

INTERSIL[Intersil Corporation]
Part No. CA316202 CA3162E CA3162
OCR Text ...OP VIEW BCD OUTPUTS 21 20 nsd 1 2 3 4 5 6 7 8 16 23 15 22 14 V+ BCD OUTPUTS DIGIT SELECT OUTPUTS MSD LSD 13 GAIN ADJ 12 INTEGRATING CAP HOLD/ BYPASS GND ZERO ADJ 11 HIGH INPUT 10 LOW INPUT 9 ZERO ADJ CAUTION...
Description A/D Converter for 3-Digit Display
A/D Converters for 3-Digit Display

File Size 555.92K  /  7 Page

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For nsd Found Datasheets File :: 148    Search Time::1.344ms    
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