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    ICE3GS03LJG

Infineon Technologies AG
Part No. ICE3GS03LJG
OCR Text ... integrated 500v startup cell ( latched and frequency jitter mode ) pg-dso-8 description the ice3gs03ljg is the 130khz version of the ice3as03ljg which is the latest version of the f3 controller for lowest standby power and low emi features...
Description Of f-Line SMPS Current Mode Controller wi th integrated 500V Startup Cell

File Size 511.35K  /  25 Page

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    GTLP36T612 GTLP36T612G GTLP36T612GX

Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
Part No. GTLP36T612 GTLP36T612G GTLP36T612GX
OCR Text ...ion. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation ...
Description 36-Bit LVTTL/GTLP Universal Bus Transceiver

File Size 77.84K  /  8 Page

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    HYMD564646AXX

Hynix Semiconductor
Part No. HYMD564646AXX
OCR Text ...ddresses and control inputs are latched on the rising edges of the clock, data, data st robes and write data masks inputs are sampled on both ris- ing and falling edges of it. the data paths are internally pipelined and 2-bit prefetched to ...
Description Unbuffered DDR SDRAM DIMM

File Size 258.99K  /  16 Page

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    CY7C9335A CY7C9335A-270AC

Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
Part No. CY7C9335A CY7C9335A-270AC
OCR Text ... (and DVB_EN is HIGH), the data latched into the input register is routed around both the NRZI decoder and the SMPTE descrambler and presented to the output register. If BYPASS is LOW at the rising edge of the CKR clock (and DVB_EN is HIGH)...
Description Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 SPECIALTY TELECOM CIRCUIT, PQFP100
SMPTE-259M/DVB-ASI Descrambler/Framer-Controller(SMPTE-259M/DVB-ASI 译码帧控制器)

File Size 82.57K  /  8 Page

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    ICS9LPR426A

Integrated Circuit Systems
Part No. ICS9LPR426A
OCR Text ...clock output. PCI clock output. latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latc...
Description Low Power Programmable Timing Control Hub⑩ for P4⑩ processor

File Size 295.77K  /  21 Page

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    LC128641-TRNGH3N LC128646-TRNGH3N LC12864A-TRNGH3N LC128641-NRNGH3N LC128646-NRNGH3N LC12864A-NRNGH3N LC128641-TRNGH3V L

List of Unclassifed Manufacturers
ETC
Part No. LC128641-TRNGH3N LC128646-TRNGH3N LC12864A-TRNGH3N LC128641-NRNGH3N LC128646-NRNGH3N LC12864A-NRNGH3N LC128641-TRNGH3V LC128646-TRNGH3V LC12864A-TRNGH3V LC128641-NRNGH3V LC128646-NRNGH3V LC12864A-NRNGH3V LC128641-TRNGHUN LC128646-TRNGHUN LC12864A-TRNGHUN LC128641-NRNGHUN LC128646-NRNGHUN LC12864A-NRNGHUN LC128641-TRNGHUV LC128646-TRNGHUV LC12864A-TRNGHUV LC128641-NRNGHUV LC128646-NRNGHUV LC12864A-NRNGHUV LC128641-TRLGS3N LC128646-TRLGS3N LC12864A-TRLGS3N LC128641-NRLGS3N LC128646-NRLGS3N LC12864A-NRLGS3N LC128641-TFLGS3N LC128646-TFLGS3N LC12864A-TFLGS3N LC128641-NFLGS3N LC128646-NFLGS3N LC12864A-NFLGS3N LC128641-TRLGS3V LC128646-TRLGS3V LC12864A-TRLGS3V LC128641-NRLGS3V LC128646-NRLGS3V LC12864A-NRLGS3V LC128641-TFLGS3V LC128646-TFLGS3V LC12864A-TFLGS3V LC128641-NFLGS3V LC128646-NFLGS3V LC12864A-NFLGS3V LC128641-NFLGH3N LC128641-NFLGH3V LC128641-NFLGHUN LC128641-NFLGHUV LC128641-NFLGSUN LC128641-NFLGSUV LC128641-NFLNH3N LC128641-NFLNH3V LC128641-NFLNHUN LC128641-NFLNHUV LC128641-TFLNH3N LC128646-TFLNH3N LC12864A-TFLNH3N LC128646-NFLNH3N LC12864A-NFLNH3N LC128641-NFLNS3N LC128641-NFLNS3V LC128641-NFLNSUN LC128641-NFLNSUV LC128641-NFNGH3N LC128641-NFNGH3V LC128641-NFNGHUN LC128641-N
OCR Text ... into display data RAM. Data is latched at falling edge of the E signal and then written into the display data RAM automatically by internal operation. 4.2.2 Output Register Output register stores the data temporarily which is read from dis...
Description LCD Module Specification

File Size 140.36K  /  20 Page

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    IDT54FCT162952CTEB IDT74FCT162952BTPV IDT73720 IDT73720A IDT73720AJ IDT73720APQF IDT73720J IDT73720PQF IDT74FCT16952ETPV

Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
Part No. IDT54FCT162952CTEB IDT74FCT162952BTPV IDT73720 IDT73720A IDT73720AJ IDT73720APQF IDT73720J IDT73720PQF IDT74FCT16952ETPV IDT74FCT16952BTPA IDT74FCT16952BTPV
OCR Text ...- Each bus can be independently latched * Byte control on all three busses * Source terminated outputs for low noise and undershoot control * 68-pin PLCC and 80-pin PQFP package * High-performance CMOS technology. DESCRIPTION: The IDT73...
Description CAP 6.8UF 20V 20% TANT SMD-6032-15 TR-7-PL SN/PB5% LOWESR-1400 FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
16-BIT TRI-PORT BUS EXCHANGER

File Size 74.95K  /  8 Page

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    K9F5608U0M- K9F5608U0M-YCB0 K9F5608U0M-YIB0

Samsung Electronics Inc
SAMSUNG[Samsung semiconductor]
Part No. K9F5608U0M- K9F5608U0M-YCB0 K9F5608U0M-YIB0
OCR Text ...to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except fo...
Description From old datasheet system
EEPROM,NAND FLASH,33MX8,CMOS,TSSOP,48PIN,PLASTIC
32M x 8 Bit NAND Flash Memory

File Size 350.10K  /  26 Page

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    K9F5608U0 K9F5608U0A K9F5608U0A-YCB0 K9F5608U0A-YIB0

Samsung Electronic
Samsung semiconductor
Part No. K9F5608U0 K9F5608U0A K9F5608U0A-YCB0 K9F5608U0A-YIB0
OCR Text ...to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except fo...
Description 32M x 8 Bit NAND Flash Memory

File Size 607.24K  /  29 Page

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    M62320FP M62320P

Mitsubishi Electric Corporation
Mitsubishi Electric Semiconductor
Part No. M62320FP M62320P
OCR Text ... the parallel data terminals is latched. When the master transmits output data after a setting in write mode, the output data is taken into the latches. * Input data latch In the read mode, the data of parallel data terminals is latched in ...
Description 8-BIT I/O EXPANDER for I2C BUS
8-BIT I/O EXPANDER for I C BUS

File Size 64.73K  /  9 Page

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