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    Cypress
Part No. CY7C1329G
OCR Text ...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- sy...
Description 2-Mb (64K x 32) Pipelined Sync SRAM

File Size 333.08K  /  16 Page

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    Cypress
Part No. CY7C1364C
OCR Text ...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- sy...
Description Memory : Sync SRAMs

File Size 330.16K  /  16 Page

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    Cypress
Part No. CY7C1365C
OCR Text ...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the firs t clock of a read cycle when emerging from a deselected state. adv 83 input- s...
Description Memory : Sync SRAMs

File Size 300.39K  /  16 Page

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    CY7C1353G-100AXC

Cypress Semiconductor
Part No. CY7C1353G-100AXC
OCR Text ...ow, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselecte...
Description 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL Architecture

File Size 402.26K  /  18 Page

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    Cypress Semiconductor, Corp.
Part No. CY7C1334H-166AXC
OCR Text ...w, the i/o pins are allowed to behave as outputs. when deasserted hi gh, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a wr ite sequence, during the first clock when emerging from a deselec...
Description 2-Mbit (64K x 32) Pipelined SRAM with NoBLArchitecture 64K X 32 ZBT SRAM, 3.5 ns, PQFP100

File Size 591.12K  /  13 Page

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    STMicroelectronics N.V.
Part No. ICSXXXXY
OCR Text .... other mode configuration pins behave identically regardless of which data interface is used. 6 ics1890 10m serial interface the 10m serial interface is an alternative serial interface between the phy and mac/repeater than the standard ...
Description Auto-Negotiation Advertisement Register (register 4 [0x04]) 自动谈判广告登记(注 [0x04]

File Size 1,726.95K  /  66 Page

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    CY7C1351G-133AXC CY7C1351G12 CY7C1351G-100AXC

Cypress Semiconductor
Part No. CY7C1351G-133AXC CY7C1351G12 CY7C1351G-100AXC
OCR Text ...ow, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the data portion of a write sequenc e, during the first clock when emergi ng from a deselected...
Description 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL Architecture

File Size 407.14K  /  20 Page

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    ST Microelectronics
Part No. MK50H28PLCC52 MK50H28Q25
OCR Text .... this pin can be programmed to behave as output rts or as programmable io pin dtr. if configured as rts, the mk50h28 will assert this pin if it has data to send and throughout the transmission of a signal unit. rclk 27 [30] i receive clock...
Description MULTI LOGICAL LINK FRAME RELAY CONTROLLER

File Size 431.87K  /  64 Page

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    TDAT042G51A-3BLL1 TDAT04622

AGERE[Agere Systems]
Part No. TDAT042G51A-3BLL1 TDAT04622
OCR Text ...me. Single-bit and enhanced RDI behave differently under the following conditions: I I Transition from error state to no error state. While in the error state, a subsequent error occurs. The single-bit error RDI does not hold the no ...
Description TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces

File Size 2,084.33K  /  310 Page

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