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QuickLogic
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| Part No. |
QL24X32B_DS QL24X32B-1PQ208I
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| OCR Text |
pASIC(R) 1 Family Very-High-Speed CMOS FPGA
pASIC HIGHLIGHTS Very High Speed - ViaLink(R) metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density - An... |
| Description |
Very-high-speed CMOS FPGA, pASIC1 family.
From old datasheet system
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| File Size |
514.47K /
8 Page |
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QuickLogic Corp.
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| Part No. |
QL3004
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| OCR Text |
pasic 3 fpga tm family high performance and high density with low cost and complete flexibiltiy pasic 3 fpga family device highlights ...r, or t-type functions. two independent set and reset inputs can asynchronously control the outpu... |
| Description |
pASIC 3 FPGA Family High Performance and High Density with Low Cost and Complete Flexibiltiy(具有低成本和充分灵活性的高性能和高密度的pASIC 3现场可编程门阵列)
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| File Size |
236.66K /
10 Page |
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QuickLogic Corp.
QuickLogic, Corp.
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| Part No. |
QL4009 QL4058
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| OCR Text |
... all rights reserved. vialink, pasic and the quicklogic logo and name are registered trademark s and quickram is a trademark of quicklogic corporation. all other company and product names are trademarks of their respective owners. printe... |
| Description |
QuickRAM ESP Family Dual-Port Embedded RAM for Extremely High Performance Functions(QuickRAM ESP系列（用于极端高性能中的嵌入式双口RAM QuickRAM ESP系列双端口嵌入式极高的性能函数的内存（QuickRAM ESP系列（用于极端高性能中的嵌入式双口RAM）的
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| File Size |
181.39K /
2 Page |
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QUICKLOGIC CORP
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| Part No. |
QL3040-0PQ240C QL3040-2PQ240I
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| OCR Text |
pasic ? 3 fpga combining high performance and high density 2-37 high performance and high density -40,000 usable pld gates with 252 i/os -...r? versions -18 dual-port ram modules, organized in user-configurable 1,152-bit blocks -5ns access t... |
| Description |
FPGA, 1008 CLBS, 40000 GATES, 250 MHz, PQFP240
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| File Size |
187.48K /
11 Page |
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it Online |
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QUICKLOGIC CORP
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| Part No. |
QL3025R-2PF144I QL3025R-2PB256C
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| OCR Text |
pasic ? 3 fpga combining high performance and high density 2-27 high performance and high density -25,000 usable pld gates with 204 i/os -...r? versions -14 dual-port ram modules, organized in user-configurable 1,152-bit blocks -5ns access t... |
| Description |
FPGA, 672 CLBS, 25000 GATES, 225 MHz, PQFP144
FPGA, 672 CLBS, 25000 GATES, 225 MHz, PBGA256
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| File Size |
152.97K /
10 Page |
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it Online |
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