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| Part No. |
XRT94L33 XRT94L33IB XRT94L333
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| OCR Text |
... data stream and also performs atm and ppp phy-layer processing. the processing of path overhead bytes within the sts-1s or tug-3s includ...ds3 de- synchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as... |
| Description |
-CHANNEL ds3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS
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| File Size |
3,662.00K /
801 Page |
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http://
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| Part No. |
XRT94L33 XRT94L332 XRT94L33IB
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| OCR Text |
... data stream and also performs atm and ppp phy-layer processing. the processing of path overhead bytes within the sts-1s or tug-3s includ...ds3 de- synchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as... |
| Description |
3-CHANNEL ds3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS
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| File Size |
3,684.65K /
810 Page |
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http://
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| Part No. |
XRT94L33IB XRT94L3306
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| OCR Text |
... data stream and also performs atm and ppp phy-layer processing. the processing of path overhead bytes within the sts-1s or tug-3s includ...ds3 de- synchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as... |
| Description |
3-CHANNEL ds3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
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| File Size |
2,228.85K /
465 Page |
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Download Datasheet |
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http://
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| Part No. |
XRT94L3307 XRT94L33IB
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| OCR Text |
... data stream and also performs atm and ppp phy-layer processing. the processing of path overhead bytes within the sts-1s or tug-3s includ...ds3 de- synchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as... |
| Description |
3-CHANNEL ds3/E3/STS-1 TO STS-3/STM-1 MAPPER - atm REGISTERS
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| File Size |
3,989.81K /
862 Page |
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MAXIM - Dallas Semiconductor
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| Part No. |
ds3183
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| OCR Text |
...nd ds3184 (ds318x) integrate atm cell/hdlc packet processor(s) with a ds3/e3 framer(s) and liu(s) to map/demap atm cells or packets into as many as four ds3/e3 physical copper lines with ds3-framed, e3-framed, or clear-channel data s... |
| Description |
Single/Dual/Triple/Quad atm/Packet PHYs with Built-In LIU
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| File Size |
3,957.74K /
386 Page |
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pmc
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| Part No. |
1990887
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| OCR Text |
... T1, E1, E3 or ds3 access to an atm Adaptation Layer One (AAL1) Constant Bit Rate (CBR) atm network. The AAL1gator-32 Reference Design is based on the 6U compact PCI standard. However, this reference design is a paper reference design only ... |
| Description |
From old datasheet system
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| File Size |
1,560.77K /
94 Page |
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Maxim
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| Part No. |
ds3161
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| OCR Text |
atm/Packet PHYs for ds3/E3/STS-1
www.maxim-ic.com
GENERAL DESCRIPTION
The ds3161, ds3162, ds3163, and ds3164 (ds316x) integrate atm cell/HDLC packet processor(s) with ds3/E3 framer(s) to map/demap atm cells or packets into as many as f... |
| Description |
Single/Dual/Triple/Quad atm/Packet PHYs for ds3/E3/STS-1
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| File Size |
3,627.41K /
385 Page |
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it Online |
Download Datasheet |
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Price and Availability
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