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				Digital Core Design
Part No.	DFPAU-DP
OCR Text	...e code: VHDL Source Code or/and verilog Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL & verilog test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic...
Description	Floating Point Arithmetic Coprocessor Double Precision
File Size	106.67K / 6 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DFPADD
OCR Text	...e code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF netlist VHDL & verilog test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic simulation...
Description	Floating Point Pipelined Adder Unit
File Size	98.71K / 3 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DFP2INT
OCR Text	...code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF netlist VHDL & verilog test bench environment Active-HDL automatic simulation macros NCSim automatic simulation macros ModelSim automatic simulatio...
Description	Floating Point To Integer Pipelined Converter
File Size	98.67K / 3 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DF6811CPU
OCR Text	...e code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF netlist VHDL & verilog test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference respo...
Description	8-bit FAST Microcontrollers Family
File Size	145.24K / 7 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DF6808
OCR Text	...code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF VHDL & verilog test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Te...
Description	8-bit FAST Microcontrollers Family
File Size	158.73K / 9 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DF6805
OCR Text	...e code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF VHDL & verilog test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Tec...
Description	8-bit FAST Microcontrollers Family
File Size	154.16K / 8 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DCORDIC
OCR Text	...e code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF netlist VHDL & verilog test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference respo...
Description	CORDIC processor
File Size	105.62K / 3 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DSPI
OCR Text	...ingle Design license for VHDL, verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist DELIVERABLES Source code: VHDL Source Code or/and verilog Source Code or/and Encrypted, or plain text EDIF netlist VH...
Description	Serial Peripheral Interface - Master/Slave
File Size	90.46K / 6 Page	View it Online	Download Datasheet

For verilog Found Datasheets File :: 524 Search Time::1.766ms
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