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Motorola
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| Part No. |
MPC755CD MPC755CE
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| OCR Text |
... L2CR clock stop bit to put the srams into a ZZ for same low power. power mode during sleep. PB3: None exists. PB3: Cannot use as ADS pin for this type of SRAM. L2 address parity cannot be None used. Y Y Y Systems requiring the ability to p... |
| Description |
RISC Microprocessor Chip Errata
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| File Size |
81.17K /
12 Page |
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it Online |
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Motorola
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| Part No. |
MPC755ED MPC755EC
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| OCR Text |
...troller and tags; external data srams -- 256K, 512K, and 1 Mbyte two-way set-associative L2 cache support -- Copy-back or write-through data cache (on a page basis, or for all L2) -- Instruction-only mode and data-only mode -- 64-byte (256K... |
| Description |
RISC Microprocessor Hardware Specifications
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| File Size |
1,046.59K /
52 Page |
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it Online |
Download Datasheet |
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Galvantech
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| Part No. |
GVT72024A8 72024A8S
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| OCR Text |
...-power CMOS process. Galvantech srams are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bu... |
| Description |
TRADITIONAL PINOUT 128K X 8 SRAM
From old datasheet system
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| File Size |
76.07K /
10 Page |
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it Online |
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Galvantech
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| Part No. |
GVT72128A8 72128A8S
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| OCR Text |
...-power CMOS process. Galvantech srams are fabricated using double-layer polysilicon, double-layer metal technology. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the ne... |
| Description |
REVOLUTIONARY PINOUT 128K X 8
From old datasheet system
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| File Size |
64.07K /
10 Page |
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it Online |
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Price and Availability
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