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Exar, Corp.
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| Part No. |
XR16M2750IM48
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| OCR Text |
...through the software setting of mcr[3]. inta is set to the active mode and op2a# output low when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# output high when mcr[3] is set to a logic 0 (default). see mcr[3].... |
| Description |
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 1 CHANNEL(S), 8M bps, SERIAL COMM CONTROLLER, PQFP48
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| File Size |
467.64K /
55 Page |
 View
it Online |
Download Datasheet
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Exar, Corp.
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| Part No. |
ST16C1551CP28
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| OCR Text |
...e and becomes active high when mcr bit-3 is set to a logic 1. int output becomes a logic high level when interrupts are enabled in the interrupt enable register (ier), and whenever the transmitter, receiver, line and/or modem status r... |
| Description |
2.97V TO 5.5V UART WITH 16-BYTE FIFO 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP28
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| File Size |
215.30K /
37 Page |
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it Online |
Download Datasheet |
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EXAR[Exar Corporation]
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| Part No. |
XR16M2752 XR16M2752IL32 XR16M2752IJ44
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| OCR Text |
...ceive interface is enabled when mcr[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when mcr[6] = 1. In the Infrared mode, the inactive state (no data)... |
| Description |
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
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| File Size |
382.21K /
52 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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