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Cypress Semiconductor Corp.
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| Part No. |
CY7C1333 7C1333 CY7C1333-66AC CY7C1333-50AC
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| OCR Text |
...age Burst Capability--linear or interleaved burst order Low (16.5 mW) standby power
Functional Description
The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-bac... |
| Description |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
From old datasheet system
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| File Size |
179.79K /
12 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1334 7C1334
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| OCR Text |
...e * Burst Capability--linear or interleaved burst order * Low (16.5 mW) standby power
Functional Description
The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back... |
| Description |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
From old datasheet system
64Kx32 Pipelined SRAM with NoBL Architecture
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| File Size |
183.37K /
11 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1335 7C1335 CY7C1335-100AC
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| OCR Text |
...ounter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * JEDEC-standard 100 TQFP pinout * "ZZ" Sleep Mode option... |
| Description |
32K X 32 CACHE SRAM, 5 ns, PQFP100
32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水线式高速缓冲存储器 RAM) 32K的32同步流水线缓存内存（32K的32同步流水线式高速缓冲存储器的RAM
From old datasheet system
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| File Size |
277.35K /
15 Page |
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Cypress
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| Part No. |
CY7C1336 7C1336
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| OCR Text |
...round counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous... |
| Description |
64K x 32 Synchronous Flow-Through 3.3V Cache RAM
From old datasheet system
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| File Size |
189.16K /
12 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1337 7C1337
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| OCR Text |
...ctable burst counter supporting interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * JEDEC-standard 100 TQFP pinout * "ZZ" Sleep Mode option... |
| Description |
32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
320.45K /
17 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1338 7C1338
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| OCR Text |
...round counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous... |
| Description |
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
From old datasheet system
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| File Size |
271.46K /
16 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1339 7C1339
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| OCR Text |
...ounter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP pinout "ZZ" Sleep Mode option and Stop ... |
| Description |
128K x 32 Synchronous-Pipelined Cache RAM(128K x 32 同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
277.19K /
15 Page |
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Maxim
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| Part No. |
MAX1181
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| OCR Text |
... digital data is presented time-interleaved on a single, parallel 10-bit output port. o Single +3V Operation o Excellent Dynamic Performance: 59dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power: 82mA (Normal Operation) 2.8mA (Sleep... |
| Description |
" Dual 10-Bit, 80Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs"
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| File Size |
836.42K /
19 Page |
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it Online |
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