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				Altera Corporation
Part No.	EPLD
OCR Text	...zed modules (LPM), Verilog HDL, vhdl, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature Usa...
Description	The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
File Size	285.65K / 42 Page	View it Online	Download Datasheet

				Actel Corporation
Part No.	COREDES-AN COREDES-AR COREDES-EV COREDES-SN COREDES-SR COREDES-UR COREDES-XX
OCR Text	...nt (IDE) Structural Verilog and vhdl Netlists (with and without I/O pads) Compatible with the Actel Designer Place-and-Route Software Tool Compiled RTL Simulation Model Supported in the Actel Libero IDE Verilog or vhdl Core Source Code Core...
Description	CoreDES
File Size	121.50K / 12 Page	View it Online	Download Datasheet

				Actel Corporation
Part No.	3DES-AN 3DES-AR 3DES-EV 3DES-SN 3DES-SR 3DES-UR 3DES-XX
OCR Text	...nt (IDE) Structural Verilog and vhdl Netlists (with and without I/O pads) Compatible with the Actel Designer Software Place-and-Route Tool Compiled RTL Simulation Model Supported in the Actel Libero IDE Verilog or vhdl Core Source Code Core...
Description	Core3DES
File Size	126.29K / 13 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	D8259
OCR Text	... DELIVERABLES Source code: vhdl Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist vhdl & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros ...
Description	Programmable Interrupt Controller
File Size	105.29K / 4 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DP8051XP03 DP8051XP
OCR Text	... DELIVERABLES Source code: vhdl Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist vhdl & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros ...
Description	Pipelined High Performance 8-bit Microcontroller ver 3.10
File Size	147.06K / 12 Page	View it Online	Download Datasheet

				ALTERA[Altera Corporation]
Part No.	MAX3000A06 MAX3000A EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A
OCR Text	...zed modules (LPM), Verilog HDL, vhdl, and other interfaces to popular EDA tools from third-party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with the Altera m...
Description	Programmable Logic Device Family
File Size	409.33K / 46 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DP8051CPU03 DP8051CPU
OCR Text	... DELIVERABLES Source code: vhdl Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist vhdl & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros ...
Description	Pipelined High Performance 8-bit Microcontroller ver 3.10
File Size	126.30K / 9 Page	View it Online	Download Datasheet

				Digital Core Design
Part No.	DP805103
OCR Text	... DELIVERABLES Source code: vhdl Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist vhdl & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros ...
Description	Pipelined High Performance 8-bit Microcontroller ver 3.10
File Size	129.16K / 9 Page	View it Online	Download Datasheet

				Actel Corporation
Part No.	COREU1PHY-AN COREU1PHY-AR COREU1PHY-EV COREU1PHY-SN COREU1PHY-SR COREU1PHY-UR COREU1PHY-XX
OCR Text	...nd Simulation Tools RTL Version vhdl Source Code Core Synthesis and Simulation Scripts Actel-Developed Testbench (vhdl) Fully Supported by Industry-Standard Simulation Tools Key Features * Standard 8-Bit, 25 MHz UTOPIA Level 1 PHY In...
Description	CoreU1PHY - UTOPIA Level 1 PHY Interface
File Size	73.76K / 8 Page	View it Online	Download Datasheet

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