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  high-fanout Datasheet PDF File

For high-fanout Found Datasheets File :: 3395    Search Time::1.657ms    
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    NB7HQ14MMNHTBG NB7HQ14MMNG NB7HQ14MMNTXG NB7HQ14M

ON Semiconductor
Part No. NB7HQ14MMNHTBG NB7HQ14MMNG NB7HQ14MMNTXG NB7HQ14M
OCR Text ...n description the nb7hq14m is a high performance differential 1:4 cml fanout buffer with a selectable equalizer receiver. when placed in series with a clock /data path operating up to 7 ghz or 10 gb/s, respectively, the nb7hq14m inputs wi...
Description 2.5V 7GHz / 10Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer w/ Selectable Input Equalizer
   2.5V 7GHz / 10Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer

File Size 1,258.39K  /  10 Page

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    NB6HQ14MMNHTBG NB6HQ14MMNG NB6HQ14MMNTXG

ON Semiconductor
Part No. NB6HQ14MMNHTBG NB6HQ14MMNG NB6HQ14MMNTXG
OCR Text ...n description the nb6hq14m is a high performance differential 1:4 cml fanout buffer with a selectable equalizer receiver. when placed in series with a clock /data path operating up to 5 ghz or 6.5 gb/s, respectively, the nb6hq14m inputs wil...
Description 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
   2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer

File Size 1,255.96K  /  11 Page

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    MK3807-01

Integrated Circuit Systems
Part No. MK3807-01
OCR Text ...nd or vcc 330a vcc=max vin=@ttl high (vcc-0.6 v) 2.0 300 a input high voltage v ih high level input pins 2 5.5 v input low voltage v il low level input pins -0.5 0.8 v output high voltage v oh vcc=min vin=vih or vil i oh = -0.1 ma, i oh ...
Description Buffer/Clock Driver

File Size 126.04K  /  9 Page

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    Micrel Semiconductor,Inc.
Part No. SY58032U07
OCR Text ...ing engine timing distribution high-end, low-skew multiprocessor synchronous clock distribution rev.: d amendment: /0 issue date: february...fanout buffer. the sy58032u is optimized to provide eight identical output copies with less than 20p...
Description ULTRA-PRECISION 1:8 FANOUT vBUFFER WITH LVPECL OUTPUTS AND INTERNAL TERMINATION

File Size 522.86K  /  8 Page

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    SY100EP14AUKGTR

Micrel Semiconductor
Part No. SY100EP14AUKGTR
OCR Text ...ption the sy100ep14au is a high-speed, 2ghz differential pecl/ecl 1:5 fanout buffer optimized for ultra-low skew applications. within device skew is guaranteed to be less than 25ps over temperature and supply voltage. the wide sup...
Description 2.5V/3.3V 1:5 LVPECL/LVECL/HSTL 2GHz Clock Driver With 2:1 Differential Input MUX

File Size 157.63K  /  8 Page

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    ICS8543BGILF

Integrated Device Technology
Part No. ICS8543BGILF
OCR Text ...tion the ics8543 is a low skew, high performance 1-to-4 differential-to-lvds clock fanout buffer. utilizing low voltage differential signaling (lvds) the ics8543 provides a low power, low noise, solution for distributing clock signals ov...
Description Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

File Size 739.45K  /  18 Page

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    Honeywell International, Inc.
NXP Semiconductors N.V.
Part No. EPA230-TD-70 EPA230-TD-100 EPA230-TD-80 EPA230-TD-75 EPA230-TD-5
OCR Text high-level output voltage v cc = min. v il = max. i oh = max 2.7 v v ol low-level output voltage v cc = min. v ih = min. i ol = max 0.5 v...fanout high-level output v cc = max. v oh = 2.7v n l fanout low-level output v cc = max. v ol = 0...
Description Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper; Temperature Range: -40°C to 85°C; Package: 8-PDIP
Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-PDIP
Logarithmic Digitally Controlled Potentiometer (XDCP™), Terminal Voltage ±5V, 100 Taps, Log Taper; Temperature Range: 0°C to 70°C; Package: 8-PDIP
Digitally Controlled Potentiometer (XDCP™); Temperature Range: 0°C to 70°C; Package: 8-PDIP
Delay Line 延迟

File Size 16.07K  /  2 Page

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    Electronic Theatre Controls, Inc.
Part No. QL4058 QL4058-3PQ208M QL4058-0PB456M QL4058-0PQ208M QL4058-0PQ240M QL4058-4PQ208M QL4058-4PB456M QL4058-3PQ240M QL4058-4PQ240M QL4058-3PB456M
OCR Text high performance & high density  58,000 usable pld gates with 252 i/os  300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos  0.35...fanout (5) 1 2 3 4 5 t pd combinatorial delay a a. these limits are derived from a representative se...
Description 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

File Size 262.96K  /  23 Page

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