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Zarlink
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| Part No. |
MT9041B
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| OCR Text |
...he 16.384MHz signal to generate four clock outputs and three frame pulse
4 Tapped Delay Line 16MHz
outputs. The C8o, C4o and C2o clocks ...phase locked to the reference. The reference frequencies are selected by the frequency control pins ... |
| Description |
T1/E1 System Synchronizer
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| File Size |
512.83K /
21 Page |
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it Online |
Download Datasheet
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Zarlink
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| Part No. |
ZL30414
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| OCR Text |
... STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 622.08 MHz Provides a CML differential clock at 155.52 MHz Provide...phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchro... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
220.94K /
23 Page |
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it Online |
Download Datasheet |
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ATMEL[ATMEL Corporation]
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| Part No. |
AT71201M DOC5328 AT71201MCRER AT71201MCREN
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| OCR Text |
...ame Readout Through One, Two or Four Outputs Data Rates Up to 4 x 40 MHz (Compatibility with 7, 4 Frames/Second) True 12-bit High Dynamic Ra...phase clock sets. Thus the sensor can be used in up to 12 main modes. The large format and high defi... |
| Description |
Atmels AT71201M is a full-frame sensor based on charge-coupled device (CCD) technology
From old datasheet system
Square Full Frame CCD of 4096 x 4096 elementary pixels 11 x 11 µm(2) size.
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| File Size |
248.75K /
20 Page |
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it Online |
Download Datasheet |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CYP15G0401DXB-BGXI
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| OCR Text |
...multi-channel bonding options ? four 8-bit channels ? two 16-bit channels ? one 32-bit channel ? n x 32-bit channel support (inter-chip) ? s...phase align buffer in transmit path ? internal phase-locked loops (plls) with no external pll compo... |
| Description |
Quad HOTLink II (TM) Transceiver; Features: Channel Bonding, 8B/10B, Redundancy, BIST, JTAG; Frequency Range: 0.2 to 1.5 Gbps; Standard: Ethernet, Fibre Channel, ESCON, DVB-ASI;
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| File Size |
713.72K /
54 Page |
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it Online |
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Price and Availability
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