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Zarlink Semiconductor
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| Part No. |
MT90221
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| OCR Text |
...provides atm framing using cell delineation according to the itu i.432 cell delineation process provides header error control (hec) veri?ation and generation, error detection, filler cell |
| Description |
Quad Inverse Multiplexing for ATM (IMA) Device with Flexible IMA and UNI Mode
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| File Size |
720.64K /
115 Page |
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AMCC
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| Part No. |
S4806CBI
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| OCR Text |
...hdlc processor provides for the delineation of hdlc frames, de-scrambling (if enabled), transparency removal and fcs error checking. the hdlc address and con- trol fields are optionally checked and can be either dropped or passed-through... |
| Description |
STS-48/STM-16 SONET/SDH Framer and ATM/POS Mapper
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| File Size |
83.40K /
4 Page |
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PMC-Sierra Inc
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| Part No. |
PM5348-RI
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| OCR Text |
..................... 9 9.6.1 cell delineation........................................................... 9 9.6.2 descrambler................................................................. 9 9.6.3 cell filter and hcs verification............... |
| Description |
SATURN USER NETWORK INTERFACE(155.52 & 51.84 MBIT/S)
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| File Size |
1,597.49K /
238 Page |
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it Online |
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Lineage Power
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| Part No. |
ATM
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| OCR Text |
... tion/checking n hec-based cell delineation n cell header single error correction/multiple error detection n cell payload (de)scrambling n direct cell mapping n idle cell insertion/deletion n out of cell delineation (ocd)/loss of cell deli... |
| Description |
Physical Layer Core(异步传输模式物理层内
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| File Size |
106.30K /
2 Page |
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Applied Micro Circuits Corp.
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| Part No. |
CS1202
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| OCR Text |
...the line side, it performs cell delineation, rx header control, descrambling, and receive cell rate adap- tation. ds3 processing the s1202 provides ds3 mapper and de-mapper functions. the ds3 mapper accepts data from an external ds3 inpu... |
| Description |
STS-12 ATM/DS3 SONET MAPPER
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| File Size |
59.42K /
2 Page |
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Cirrus Logic, Inc.
CRYSTAL SEMICONDUCTOR CORP
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| Part No. |
CS4330-BS CS4330-KS CS4333-KS CS4331-KS CS4331-BS CS4333-BS CS4331-KSR
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| OCR Text |
... (lrck) defines the channel and delineation of data and the serial clock (sclk) clocks audio data into the input data buffer. the cs4330, cs4331 and cs4333 differ in the serial data for- mat as shown in figures 4-7. the master clock (mclk) ... |
| Description |
8 Pin Stereo D/A Converter for Digital Audio SERIAL INPUT LOADING, 18-BIT DAC, PDSO8
8 Pin Stereo D/A Converter for Digital Audio 8引脚立体声D / A的数字音频转换器
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| File Size |
1,081.14K /
38 Page |
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it Online |
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