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  pwd Datasheet PDF File

For pwd Found Datasheets File :: 1120    Search Time::11.172ms    
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    ICS9148-58 ICS9148F-58 AV9148F-58

ICST[Integrated Circuit Systems]
Part No. ICS9148-58 ICS9148F-58 AV9148F-58
OCR Text ... 0 1--Tristate all outputs 4 pwd 0 Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desi...
Description Frequency generator and integrated buffers for PENTIUM/PRO
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Single Chip, SIS 5600B 133MHz System Clock with AGP Clocks

File Size 446.31K  /  14 Page

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    ICS9148-60 ICS9148YF-60

Integrated Device Technology, Inc.
ICST[Integrated Circuit Systems]
Part No. ICS9148-60 ICS9148YF-60
OCR Text ...um ON 11 - Tristate all outputs pwd 0 Byte 5: Bit 7 6 5 Pin# 4 11 10 8 7 6 5 Pin Name PCICLK_F PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 pwd 1 1 1 0 1 1 1 1 Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled E...
Description 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 SSOP-28
Frequency Generator & Integrated Buffers
Pentium/ProTM System Clock Chip
BX Main Clock, 2 Chip Clock, Supports 66.6 - 100MHz

File Size 276.81K  /  10 Page

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    ICS9148-82 ICS9148YF-82

ICST[Integrated Circuit Systems]
Part No. ICS9148-82 ICS9148YF-82
OCR Text ...Running 1- Tristate all outputs pwd 0 Bit 6:4 Note1 Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these shoul...
Description Frequency Generator & Integrated Buffers for PENTIUM/ProTM

File Size 792.29K  /  16 Page

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    ICS9148-93 ICS9148F-37

ICST[Integrated Circuit Systems]
Part No. ICS9148-93 ICS9148F-37
OCR Text ...0 1- -Triunninall outputs state pwd 0 Note 1. Default at Power-up will be for latched logic inputs, as defined by Bit 3. XXX Note 1 I2C is a trademark of Philips Corporation 0 0 0 0 4 ICS9148-93 Advance Information Byt...
Description Frequency Generator & Integrated Buffers for PENTIUM/ProTM

File Size 623.83K  /  14 Page

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    ICS9148B-04 ICS9148BF-04 ICS9148-04

ICST[Integrated Circuit Systems]
Part No. ICS9148B-04 ICS9148BF-04 ICS9148-04
OCR Text ... Select Register (default = 0) pwd 0 Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desire...
Description Clock Synthesizer
Frequency Generator & Integrated Buffers for PENTIUM/ProTM

File Size 577.55K  /  14 Page

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    MAX3664 MAX3664ESA 1228 MAX3664E_D MAX3664E/D

MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
Part No. MAX3664 MAX3664ESA 1228 MAX3664E_D MAX3664E/D
OCR Text ...nt, 50% duty cycle, 1-0 pattern pwd 100A to 300A peak input current, 50% duty cycle, 1-0 pattern in CIN = 0.3pF (Note 6), IIN = 0 CIN = 1.1pF (Note 6), IIN = 0 80 55 73 86 200 nA 6 SYMBOL BW-3dB CONDITIONS Relative to gain at 10MHz MIN TYP ...
Description 622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
From old datasheet system
622Mbps / Ultra-Low-Power / 3.3V Transimpedance Preamplifier for SDH/SONET

File Size 235.18K  /  12 Page

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