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CIRRUS[Cirrus Logic]
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| Part No. |
CS22210
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| OCR Text |
...rupt * Variable endpoint buffer depths providing maximum flexibility for endpoint configurations * Flexible configuration programming via EEPROM or firmware download * Remote host wakeup Chip Processing and Packaging * 208 MQFP package and ... |
| Description |
WIRELESS PCI/USB CONTROLLER
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| File Size |
310.17K /
31 Page |
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CIRRUS[Cirrus Logic]
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| Part No. |
CS22230
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| OCR Text |
...rupt * Variable endpoint buffer depths providing maximum flexibility for endpoint configurations * Flexible configuration programming via EEPROM or firmware download * Remote host wakeup
CS22230 Mini PCI / USB Wireless Controller
2 of... |
| Description |
WIRELESS PCI/USB CONTROLLER
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| File Size |
249.84K /
29 Page |
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Download Datasheet
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CYPRESS[Cypress Semiconductor] Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
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| Part No. |
CYM1846V33PZ-35C CYM1846V33 CYM1846V33P8-12C CYM1846V33P8-15C CYM1846V33P8-20C CYM1846V33P8-25C CYM1846V33P8-35C CYM1846V33PM-12C CYM1846V33PM-15C CYM1846V33PM-20C CYM1846V33PM-25C CYM1846V33PM-35C CYM1846V33PZ-12C CYM1846V33PZ-15C CYM1846V33PZ-20C CYM1846V33PZ-25C
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| OCR Text |
...ere modules with alternate word depths can be interchanged.
Functional Description
The CYM1846V33 is a high-performance 3.3V 16-megabit static RAM module organized as 512K words by 32 bits. This
Logic Block Diagram
PD0 PD1 PD2 PD3 O... |
| Description |
Memory 内存 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 25 ns, PZMA72 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 25 ns, PSMA72 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 12 ns, PSMA72 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 12 ns, PZMA72 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 20 ns, PSMA72 512K x 32 3.3V Static RAM Module 512K X 32 MULTI DEVICE SRAM MODULE, 15 ns, PZMA72
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| File Size |
215.92K /
8 Page |
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INTERSIL[Intersil Corporation]
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| Part No. |
HC6094IN HC6094
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| OCR Text |
... with different PARs. The notch depths for each DMT waveform are averaged to give an MTPR number.
5
HC6094 Shift Register Format
Each write operation to a control register involves 16 bits of data. The CS- signal must be enabled low ... |
| Description |
ADSL Analog Front End Chip
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| File Size |
50.62K /
9 Page |
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it Online |
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Price and Availability
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