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ST Microelectronics
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| Part No. |
ST20190
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| OCR Text |
...l level functions (such as cell delineation, insertion/ extraction of idle cells, payload scrambling, HEC check) and data frame generation. The controller is able to run in different rate-adaptive modes as defined by the operator. During op... |
| Description |
ADSL2 and ADSL Modem Chipset for CPE Applications with Utopia II Interface
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| File Size |
92.57K /
7 Page |
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it Online |
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PMC-Sierra Inc
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| Part No. |
PM7375-SC
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| OCR Text |
...45 9.3.1 9.3.2 9.3.3 9.3.4 CELL delineation.........................................................................................45 CELL FILTER AND HEC VERIFICATION..........................................................46 GFC EXTRACTI... |
| Description |
LOCAL ATM SAR & PHYSICAL LAYER
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| File Size |
2,505.25K /
430 Page |
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it Online |
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PMC-Sierra, Inc.
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| Part No. |
PM5945
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| OCR Text |
...s to the ATM payload using cell delineation. Header check sequence (HCS) error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an Uncorrectable HCS er... |
| Description |
CONN
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| File Size |
1,461.86K /
75 Page |
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it Online |
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Cirrus Logic, Inc.
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| Part No. |
CS4328-BS CS4328-BP CS4328-KP
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| OCR Text |
...nd LRCK defines the channel and delineation of data. The DAC supports four serial data formats which are selected via the digital input format pins DIF0 and DIF1. The different formats control the relationship of LRCK to SDATAI and the edge... |
| Description |
18-Bit, Stereo D/A Converter for Digital Audio
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| File Size |
828.36K /
31 Page |
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it Online |
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Cypress
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| Part No. |
CY7C955-NC CY7C955-NI
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| OCR Text |
...TM Cell Processor has lost cell delineation. Receive Interrupt: This active HIGH signal is aligned with the RCLK byte-rate clock and signals the presence of LAIS, PAIS, LOS, LOF, LOP, or LCD. Receive Start Of GFC: This output indicates the ... |
| Description |
AX ATM-SONET/SDH Transceiver
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| File Size |
468.92K /
78 Page |
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it Online |
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