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IDT[Integrated Device Technology]
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| Part No. |
IDT5T9316NLI IDT5T9316 IDT5T9316NLI8
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| OCR Text |
...UTPUT CONTROL Q6 Q6
A2 A2
0
OUTPUT CONTROL
Q7 Q7
SEL
OUTPUT CONTROL
Q8 Q8
G2
OUTPUT CONTROL
Q9 Q9
OUTPUT CONTROL
Q10 Q10
OUTPUT CONTROL
Q11 Q11
OUTPUT CONTROL
Q12 Q12
OUTPUT CONTROL
Q13 ... |
| Description |
2.5V LVDS 1:16 CLOCK BUFFER TERABUFFER II
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| File Size |
92.92K /
12 Page |
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it Online |
Download Datasheet
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V927 IDT5V927PGI8
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| OCR Text |
...and outputs) Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) Low jitter PLL bypass for testing and power-down control (S1 = H, S0 = H, powers part down <500A) Available in TSSOP package
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| Description |
Quad Output Clock Generator
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| File Size |
44.37K /
6 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V994PFI IDT5V994 IDT5V994JI IDT5V994PFGI IDT5V994PFI8
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| OCR Text |
...AM
sO E
Skew Select 3 3 1F1:0 PE TEST Skew Select REF PLL FB Skew Select 3 3 3F1:0 3 3 2F1:0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
Skew Select 3 3 4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
4Q0 ... |
| Description |
3.3V Programmable Skew PLL Clock Driver TurboClock Plus
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM PLUS
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| File Size |
65.67K /
9 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V995PFI IDT5V995 IDT5V995PFGI
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| OCR Text |
... 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sO... |
| Description |
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
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| File Size |
71.68K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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