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Sanyo Electric Co.,Ltd.
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| Part No. |
LC863364A LC863348A
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| OCR Text |
...line number can be set for each row independently (rows can be overlapped) - horizontal display start position can be set for each row independently - horizontal pitch (bit 9 - 16) *1 and vertical pitch (bit-32) can be set for each row i... |
| Description |
8-Bit Single-Chip Microcontroller with On-Chip 64K Bytes ROM and 640 Bytes RAM(8浣????井?у????甯??涓?4K瀛??ROM??40瀛??RAM锛?
8-Bit Single-Chip Microcontroller with On-Chip 48K Bytes ROM and 640 Bytes RAM(8浣????井?у????甯??涓?8K瀛??ROM??40瀛??RAM锛?
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| File Size |
655.63K /
20 Page |
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it Online |
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| Part No. |
GM71V17400CT-6 GM71V17400CCL
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| OCR Text |
...s inputs data-input/data-output row address strobe column address strobe read/write enable output enable power (+3.3v) ground ordering information type no. access time package gm71v(s)17400cj/clj-5 gm71v(s)17400cj/clj-6 gm71v(s)17400cj/clj... |
| Description |
x4 Fast Page Mode DRAM
4Mx4|3.3V|2K|5/6/7|FP/EDO DRAM - 16M
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| File Size |
104.91K /
10 Page |
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it Online |
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HYNIX SEMICONDUCTOR INC
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| Part No. |
HY5DU28822LT-K
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| OCR Text |
...cas activity. a0 ~ a11 address row address : a0 ~ a11, column address : a0 ~ a9, ap flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operations. refer function truth tabl... |
| Description |
16M X 8 DDR DRAM, PDSO66
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| File Size |
84.91K /
10 Page |
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it Online |
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Molex Electronics Ltd.
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| Part No. |
0702871100
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| OCR Text |
... header, breakaway, dual row, vertical, with retention pin, 8 circuits, 6.10mm (.240") mating pin length, 0.38m (15") gold (au) selective plating documents: 3d model product specification ps-70280 ... |
| Description |
2.54mm (.100) Pitch C-Grid? Header, Breakaway, Dual Row, Vertical, with RetentionPin, 8 Circuits, 6.10mm (.240) Mating Pin Length, 0.38μm (15μ) Gold (Au) Selective
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| File Size |
308.36K /
6 Page |
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it Online |
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NANYA TECHNOLOGY CORP
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| Part No. |
NT5DS16M16BW-6K
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| OCR Text |
...are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for progr... |
| Description |
16M X 16 DDR DRAM, 0.7 ns, PBGA60
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| File Size |
1,341.90K /
80 Page |
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it Online |
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NXP
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| Part No. |
AN10935
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| OCR Text |
...ess strobe emc_ras_n - sdram row address strobe sdram row address strobe emc_dqm[0] - emc_dqm[3] - sdram byte write mask 0 through 3 sdram byte write mask 0 through 3 an10935 all information provided in this document is su... |
| Description |
Using SDR/DDR SDRAM memories
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| File Size |
368.49K /
47 Page |
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it Online |
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Alliance Semiconductor
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| Part No. |
AS4C4M16S-6TIN
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| OCR Text |
...( m a x .) 5.4/5.4ns tras row active time(min.) 42/49 ns trc row cycle time(min.) 60/63 ns part number frequenc y package as4c4m16s - 6t c n 166mhz tsop ii as4c4m16s - 6ti n 166 mhz tsop i... |
| Description |
64Mb / 4M x 16 bit Synchronous DRAM
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| File Size |
3,342.14K /
53 Page |
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it Online |
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