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Intersil
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| Part No. |
CD82C52 8501501XA
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| OCR Text |
... in the Modem Control Register (mcr). This signal is cleared (high) by writing a logic 0 in the DTR bit in the mcr or whenever a reset (RST = high) is applied to the 82C52. REQUEST TO SEND: The RTS signal can be set (low) by writing a logic... |
| Description |
CMOS Serial Controller Interface
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| File Size |
259.96K /
20 Page |
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EXAR[Exar Corporation]
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| Part No. |
XR16C2450IP XR16C2450IM XR16C2450IJ XR16C2450
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| OCR Text |
...through the software setting of mcr[3]. INTA is set to the active mode and OP2A# output to a logic 0 when mcr[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when mcr[3] is set to a logic 0 (default). UART... |
| Description |
2.97V TO 5.5V DUART
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| File Size |
318.66K /
31 Page |
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it Online |
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EXAR[Exar Corporation]
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| Part No. |
XR16C864 XR16C864IQ XR16C864CQ
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| OCR Text |
...through the software setting of mcr[3]. INTA is set to the active mode when mcr[3] is set to a logic 1. INTA is set to the three state mode when mcr[3] is set to a logic 0 (default). See mcr[3]. When 16/68# pin is at logic 0 for Motorola bu... |
| Description |
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
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| File Size |
309.36K /
51 Page |
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it Online |
Download Datasheet
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