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latency Datasheet PDF File

For latency Found Datasheets File :: 13968 Search Time::1.5ms
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				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc. INTEGRATED DEVICE TECHNOLOGY INC
Part No.	ICS9248-157 ICS9248YF-157-T ICS9248YF-157LF-T AV9248F-157-T
OCR Text	...nd the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " l...
Description	Frequency timing generator for Pentium II system Two Chip Solution for Pentium II using ALI 1621/1632M Style Chipsets Frequency Timing Generator for Pentium II Systems 139.65 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 0.209 INCH, SSOP-28
File Size	149.58K / 11 Page	View it Online	Download Datasheet

				Integrated Silicon Solu...
Part No.	IS46LR32800F IS46LR32800F-6BLA2
OCR Text	...ess key programs - cas latency 2, 3 (clock) - burst length (2, 4, 8, 16) - burst type (sequential & interleave) ? fully differential clock inputs (ck, /ck) ? all inputs except data & dm are sampled at...
Description	2M x 32Bits x 4Banks Mobile DDR SDRAM
File Size	1,411.27K / 47 Page	View it Online	Download Datasheet

				Integrated Silicon Solu...
Part No.	IS46LR32640A
OCR Text	...ess key programs - cas latency 2, 3 (clock) - burst length (2, 4, 8) - burst type (sequential & interleave) ? fully differential clock inputs (ck, /ck) ? all inputs except data & dm are sampled at th...
Description	16M x 32Bits x 4Banks Mobile DDR SDRAM
File Size	1,180.84K / 43 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems] http://
Part No.	ICS9248-192 ICS9248YG-192-T
OCR Text	...nd the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V PCI clock outputs, free running selectable Ground for PCI clock outputs 3.3V power for the PCI clock outputs Selects 24MHz (0) or 48MHz (1) output ...
Description	Single Chip Clock for Transmeta Frequency Timing Generator for Transmeta Systems
File Size	102.92K / 12 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-20 ICS9248F-20 AV9248F-20
OCR Text	...end of their current cycle. The latency of Power Down will not be greater than 3ms. CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will con...
Description	Pentium/PRO system clock chip Pentium/ProTM System Clock Chip
File Size	340.17K / 11 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. ICST[Integrated Circuit Systems]
Part No.	ICS9248-50 ICS9248YG-50-T ICS9248YG-50LF-T
OCR Text	...nd the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " l...
Description	100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 6.10 MM, 0.65 MM PITCH, TSSOP-28 Frequency Timing Generator for Pentium II Systems 频率的奔腾II系统时序发生
File Size	260.46K / 11 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] http://
Part No.	ICS9248-55 ICS9248BF-55
OCR Text	...quirements SIGNAL SIGNAL STATE latency No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max CPU_ STOP# PCI_STOP# PD# 0 (Disabled) 2 1 (Enabled) 1 0 (Disabled) 2 1 (Enabled) 1 1 (Normal Operation) 3 0 (Power Down) 4 Notes. 1...
Description	Pentium/Pro/IITM System Clock Chip 奔腾/专业/ IITM系统时钟芯片 BX Main Clock, Supports 66.6 - 100MHz
File Size	268.23K / 10 Page	View it Online	Download Datasheet

				TE Connectivity, Ltd. Integrated Device Technology, Inc. ICST[Integrated Circuit Systems]
Part No.	ICS9248-56 ICS9248YG-56-T ICS9248YG-56LF-T ICS9248F-56
OCR Text	...nd the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " l...
Description	Peripheral IC 外围芯片 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 4.40 MM, 0.65 MM PITCH, TSSOP-28 20-Bit Buffers/Drivers With 3-State Outputs 56-TSSOP -40 to 85 Frequency Generator & Integrated Buffers Frequency Timing Generator for Pentium II Systems BX Mobile Main Clock with Real Time Spread, Supports 66.6 - 100MHz
File Size	262.48K / 11 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-61 ICS9248F-61 AV9248F-61
OCR Text	...nd the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " l...
Description	Frequency timing generator for Pentium II system BX Mobile Main Clock with Power Management Feature, Supports 66.6 - 100MHz Frequency Timing Generator for Pentium II Systems Frequency Generator & Integrated Buffers
File Size	288.93K / 9 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. ICST[Integrated Circuit Systems]
Part No.	ICS9248-65 ICS9248YF-65 9248YF-65
OCR Text	... outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. Power Management Requirements: Late ncy Singal Singal State 1 (normal operation)...
Description	PROC SPECIFIC CLOCK GENERATOR, PDSO48 SSOP-48 20-Bit Buffers/Drivers With 3-State Outputs 56-TSSOP -40 to 85 Frequency Generator & Integrated Buffers Frequency Timing Generator for PENDIUM II Systems 820 Single Chip Clock, Supports 100 - 133MHz
File Size	263.77K / 10 Page	View it Online	Download Datasheet

For latency Found Datasheets File :: 13968 Search Time::1.5ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | <11> | 12 | 13 | 14 | 15 |