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飞思卡尔半导体(中国)有限公司
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| Part No. |
56F80XXBLUG
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| OCR Text |
... 56800e core is based on a dual harvard-style architecture consisting of th ree execution units operating in parallel, allowing as many as six operations per instruction cycle. the mc u-style programming model and optimized instruction... |
| Description |
Digital Signal Controller Product Brief
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| File Size |
109.46K /
12 Page |
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it Online |
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Motorola
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| Part No. |
DSP56858PBD
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| OCR Text |
...ose i/o 56858 memory features ? harvard architecture permits up to three simultaneous accesses to program and data memory ? on-chip memory C 80 kb program ram C 48 kb data ram C2 kb boot rom ? off-chip memory expansion (emi) C access up to... |
| Description |
56858 Digital Signal Processor Product Brief
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| File Size |
78.62K /
2 Page |
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it Online |
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Motorola
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| Part No. |
DSP56F801PB
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| OCR Text |
...800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators including exten... |
| Description |
56F801 16-bit Hybrid Controller Product Brief
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| File Size |
40.99K /
4 Page |
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it Online |
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Motorola
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| Part No. |
DSP56F802PB
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| OCR Text |
...800 family dsp engine with dual harvard architecture as many as 40 million instructions per second (mips) at 80 mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) two 36-bit accumulators including extensi... |
| Description |
56F802 16-Bit Hybrid Controller Product Brief
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| File Size |
46.91K /
4 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
DSP56F803PB
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| OCR Text |
...800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16 - bit parallel multiplier-accumulator (mac) ? two 36 - bit accumulators, including ... |
| Description |
56F803 16-Bit Hybrid Controller Product Brief
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| File Size |
44.63K /
4 Page |
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it Online |
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Atmel
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| Part No. |
TSC21020F 21020F
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| OCR Text |
...ting-Point-Processor D Off-Chip harvard Architecture Maximizes Signal Processing Performance D 50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution D 60 MFLOPS Peak, 40 MFLOPS Sustained Performance D 1024-Point Complex FFT Benchmark : 0.... |
| Description |
Radiation Tolerant 32/40?Bit IEEE Floating?Point DSP Microprocessor
From old datasheet system
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| File Size |
485.14K /
37 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
DSP56F805PB
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| OCR Text |
...800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators, including exte... |
| Description |
56F805 16-Bit Hybrid Controller Product Brief
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| File Size |
46.84K /
4 Page |
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it Online |
Download Datasheet |
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Price and Availability
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