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  retiming Datasheet PDF File

For retiming Found Datasheets File :: 446    Search Time::2.609ms    
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    Maxim
Part No. MAX3892EVKIT
OCR Text ...This also enables the SCLKO for retiming the 2.5Gbps serial data. See Figure 1 for other states of the MODE pin. Install none or one of jumpers JU8, JU9, or JU10. 5) Connect PCLKO lines at J22 and J23 to PCLKI inputs at J12 and J11 (PCLKO+ ...
Description Evaluation Kit for the MAX3892
From old datasheet system

File Size 672.48K  /  10 Page

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    ST Microelectronics
Part No. ADE3000T
OCR Text .......................... 29 Sync retiming Block .......................................................................................................... 30 Sync Measurement Block ...............................................................
Description LCD DISPLAY ENGINES WITH INTEGRATED DVI ADC AND YUV PORTS

File Size 514.78K  /  89 Page

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    MAX3634ETM MAX3634

Maxim Integrated Products, Inc.
Part No. MAX3634ETM MAX3634
OCR Text ...e clock by eight for use in the retiming circuitry. For correct operation, the REFCLK input must be connected to the OLT byte-rate reference clock, which must be equal to 1/8th the serial data rate, and must have a 40% to 60% duty cycle. Th...
Description Dual High-Speed Differential Driver & Receiver 16-TSSOP -40 to 85
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications

File Size 310.83K  /  8 Page

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    AD60007

Analog Devices
Part No. AD60007
OCR Text retiming AD808 frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD808 acquires frequency and phase lock on input data using two...
Description 622 Mbps Low Power Post-Amp/Clock and Data Recovery IC

File Size 146.47K  /  13 Page

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    Agilent(Hewlett-Packard...
HP[Agilent(Hewlett-Packard)]
Agilent (Hewlett-Packard)
Part No. RGR1551-ST RGR1551-SC RGR1551-FP RGR1551-DN RGR1551
OCR Text ...uding a clock recovery and data retiming function. It is designed with a multimode fiber pigtail to allow maximum flexibility in connector options. The interface amplifier is ac coupled to the preamplifier circuit. Terminating the Outputs T...
Description Fiber Optic “Light to Logic?Receiver with Clock Recovery
Fiber Optic “Light to LogicReceiver with Clock Recovery
Fiber Optic “Light to Logic” Receiver with Clock Recovery
Fiber Optic Light to Logic Receiver with Clock Recovery
Fiber Optic Light to LogicReceiver with Clock Recovery
Fiber Optic “Light to Logic Receiver with Clock Recovery

File Size 95.35K  /  6 Page

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    AD[Analog Devices]
Part No. AD805 AD805BN
OCR Text retiming Permits CCITT G.958 Type A Jitter Tolerance Permits CCITT G.958 Type B Jitter Transfer Random Jitter: 0.6 rms Pattern Jitter: Virtually Eliminated Jitter Peaking: Fundamentally None Acquisition: 30 Bit Periods Accepts NRZ Data with...
Description DATA retiming PHASE LOCKED LOOP

File Size 308.20K  /  12 Page

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    http://
PANASONIC[Panasonic Semiconductor]
Part No. MN89201
OCR Text ...SYNC, and XBLANK signals have a retiming at the rising edge of this clock signal. 58 59 60 61 XHSYNC XVSYNC XBLANK XENRST O O O O Horizontal synchronizing output signal (Active "L") Vertical synchronizing output signal (Active "...
Description VGA-NTSC Scan Converter

File Size 62.80K  /  11 Page

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    VSC8222 VSC8223

Vitesse Semiconductor Corporation
Part No. VSC8222 VSC8223
OCR Text ...SC7940 LD VSC8222 Data retiming For more information on Vitesse Products visit the Vitesse web site at www.vitesse.com or contact Vitesse Sales at (800) VITESSE or sales@vitesse.com 741 Calle Plano Camarillo, CA 93012, USA Tel:...
Description (VSC8223) Multi-Rate SONET/SDH / Fibre Channel and Gigabit Rthernet CDR
MULTI-RATE SONET/SDH, FIBRE CHANNEL, AND GIGABIT ETHERNET CDR

File Size 384.47K  /  2 Page

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    ICS2059-02 ICS205902 ICS2059GI-02 ICS2059GI-02T

Integrated Circuit Syst...
ICS
Integrated Circuit Systems
Part No. ICS2059-02 ICS205902 ICS2059GI-02 ICS2059GI-02T
OCR Text ...place a more costly hybrid VCXO retiming module. A dual input mux is also provided. By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the input clock. Through selection of ...
Description Clock Multiplier and Jitter Attenuator
From old datasheet system

File Size 135.38K  /  11 Page

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    CMLMICRO[CML Microcircuits]
Part No. MX604
OCR Text ...Line Equalization 1200bps Data retiming Facility can eliminate external UART Low Voltage Operation (3.3 to 5.0V) v.23 Compatible Modem PRELIMINARY INFORMATION APPLICATIONS Low Power Operation 1mA typ. @ 3.3V Operating Mode 1A typ...
Description v.23 Compatible Modem

File Size 172.07K  /  18 Page

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