| |
|
 |
Exar, Corp.
|
| Part No. |
ST16C2450IJ44-F
|
| OCR Text |
...hrough the software settin g of mcr[3]. inta is set to the active mode and op2a# output to a logic 0 when mcr[3] is set to a logic 1. inta is set to the three state mode and op2a# to a logic 1 when mcr[3] is set to a logic 0 (default). ... |
| Description |
2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 GREEN, PLASTIC, LCC-44
|
| File Size |
368.00K /
32 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Circuit Syst...
|
| Part No. |
ICS2002 ICS2002Y
|
| OCR Text |
...are reset, and in unaffected by mcr (see below). ir80 chip control bits 7:3 - reserved bit 2 - sound source emulation mode (ssmode) this bit sets the chip to operate in sound source emu- lation mode. in sound source emulation mode, the two ... |
| Description |
Wavedec Digital Audio Codec Wavedec数字音频编解码器
|
| File Size |
555.04K /
21 Page |
View
it Online |
Download Datasheet |
| |
|
|
N.A.
|
| Part No. |
TG16C554CQ TG16C554
|
| OCR Text |
...s the TG16C554CQ operates under mcr bit-3 control having IRQSEL internally bonded to GND. The TG16C554 is ideally suited for PC, embedded systems and Networking applications, such as high speed COM ports or internal modems. The TG16C554 is ... |
| Description |
The TG16C554 is a quad-channel high performance UART
offering data rates up to 1.5Mbps.
|
| File Size |
107.05K /
24 Page |
View
it Online |
Download Datasheet |
| |
|
|
Philips
|
| Part No. |
SC16C652 SC16C652-02
|
| OCR Text |
...TB. INTA, INTB are enabled when mcr bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and is active when an interrupt condition exists. Interrupt conditions include: receiver errors, available receive... |
| Description |
Dual UART with 32 bytes of transmit and receive FIFOs
From old datasheet system
|
| File Size |
168.79K /
41 Page |
View
it Online |
Download Datasheet |
| |
|
|
EXAR[Exar Corporation]
|
| Part No. |
XR16L2751 XR16L2751IM XR16L2751CM
|
| OCR Text |
...through the software setting of mcr[3]. INTA is set to the active mode and OP2A# output to a logic 0 when mcr[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when mcr[3] is set to a logic 0. See mcr[3]. Wh... |
| Description |
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
|
| File Size |
310.38K /
52 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
