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IDT
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| Part No. |
IDT71V2558SA IDT71V2558S IDT71V2556SA IDT71V2556S
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| OCR Text |
...w) and ADV/LD low at the rising edg e of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. Synchronous active high chip enable. CE2 is used... |
| Description |
128K x 36, 256K x 18 3.3V Synchronous ZBT? SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
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| File Size |
513.18K /
28 Page |
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it Online |
Download Datasheet
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| Part No. |
K7D161888B-HC330 K7D161888B-HC250 K7D161888B-HC300
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| OCR Text |
...registers off the second rising edg e of k clock. during ddr read operations, addresses and controls are registered at the first rising edge of k clock, and then the in ternal array is read twice between first and second rising edges of k ... |
| Description |
1M X 18 DDR SRAM, 0.2 ns, PBGA153
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| File Size |
377.60K /
16 Page |
View
it Online |
Download Datasheet
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Price and Availability
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