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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1360A-150AC CY7C1360A-150AI CY7C1360A-150AJC CY7C1360A-150AJI CY7C1360A-200AC CY7C1362A-225AC CY7C1362A-225AJC CY7C1360A-200AI CY7C1360A-200AJC CY7C1360A-200AJI CY7C1362A-166BGI CY7C1362A-200AJC CY7C1362A-166AJC CY7C1362A-150AJC CY7C1362A-166BGC CY7C1362A-200BGI CY7C1362A-200BGC CY7C1360A-166AC CY7C1362A-150BGC CY7C1360A-200BGC CY7C1362A-225BGC
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| OCR Text |
..., 6b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (t/aj version) 43 (ta/a version) a0 a1 a input- synchronous addresses : these inputs are registered and must meet the set-up ... |
| Description |
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM 256K X 36 CACHE SRAM, 3 ns, PBGA119
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM 512K X 18 CACHE SRAM, 2.5 ns, PBGA119
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| File Size |
566.05K /
28 Page |
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Sumida, Corp.
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| Part No. |
CY7C1347D-200BGC CY7C1347D-250BGC CY7C1347D-166AC CY7C1347D-200AC
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| OCR Text |
..., 5b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set-up and hold times around the rising edg... |
| Description |
x36 Fast Synchronous SRAM x36快速同步SRAM
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| File Size |
522.49K /
24 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1363A-133AJI CY7C1363A-133AI CY7C1361A-133AI CY7C1361A-133BGI CY7C1361A-117BGI CY7C1361A-133AJI CY7C1361A-117AI CY7C1361A-117AJI CY7C1361A-100BGI CY7C1361A-100AI CY7C1361A-100AJI CY7C1363A-117BGI
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| OCR Text |
..., 6b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (aj version) 43 (a version) a0 a1 a input- synchronous addresses : these inputs are registered and must meet the set-up and h... |
| Description |
256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
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| File Size |
824.59K /
26 Page |
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it Online |
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Galvantech
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| Part No. |
GVT71256T18 71256T18
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| OCR Text |
...5B, 2C, 3C, 5C, 6C, 2r, 6R, 2T, 3t, 5T, 6T 5L 3G
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
TQFP PINS
37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 93 94
SYMBOL
A0 A1 A
TYPE
Input-
DESCRIPTION
Ad... |
| Description |
256K X 18 SYNCHRONOUS TAG SRAM
From old datasheet system
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| File Size |
269.04K /
24 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
GVT71512C18TA-4.4 GVT71512C18TA-6.7 GVT71512C18TA-5
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| OCR Text |
...b, 6b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (t version) 43 (ta version) a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set up and ... |
| Description |
256K x 36/512K x 18 Pipelined SRAM
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| File Size |
314.22K /
27 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1355A-117BGC CY7C1355A-117BGI CY7C1357A-100AC CY7C1357A-100AI CY7C1357A-133AC CY7C1355A-100BGC CY7C1355A-133AC CY7C1355A-117AC
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| OCR Text |
..., 2c, 3c, 5c, 6c, 4g, 2r, 6r, 3t, 4t, 5t a0, a1, a input- synchronous synchronous address inputs : the address register is triggered by a combination of the rising edge of clk, adv/ld low, cen low and true chip enables. a0 and a1 are ... |
| Description |
256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7 ns, PQFP100
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| File Size |
570.54K /
28 Page |
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it Online |
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Galvantech
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| Part No. |
GVT71256DA18 GVT71128DA36 DA3618
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| OCR Text |
...3, 32, 100, 3C, 5C, 6C, 2r, 6R, 3t, 4T, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 5T 5L 5G 3G 3L 4M 4H 93 94 95 96 87 88
InputAddresses: These inputs are registered and must meet the setup and hold times Synchronous around the rising edge o... |
| Description |
128K X 36/256K X 18 SYNCHRONOUS SRAM
From old datasheet system
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| File Size |
246.90K /
24 Page |
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it Online |
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Galvantech
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| Part No. |
GVT71256D36 71256D36
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| OCR Text |
...2, 100, 2C, 3C, 5C, 6C, 2r, 6R, 3t, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 4T, 5T 92 (T Version) 43 (TA Version) 5L 5G 3G 3L 4M 4H 93 94 95 96 87 88
InputAddresses: These inputs are registered and must meet the setup and hold times Synch... |
| Description |
256K X 36/512K X 18 SYNCHRONOUS SRAM
From old datasheet system
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| File Size |
256.13K /
25 Page |
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it Online |
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http://
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| Part No. |
GVT71512C18T-6.7 GVT71512C18B-4.4 GVT71512C18B-6.7
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| OCR Text |
...b, 6b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (t version) 43 (ta version) a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set up and ... |
| Description |
256K x 36/512K x 18 Pipelined SRAM
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| File Size |
310.03K /
27 Page |
View
it Online |
Download Datasheet |
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http://
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| Part No. |
GVT71512ZC18B-7.5I GVT71256ZC36B-6I
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| OCR Text |
..., 2c, 3c, 5c, 6c, 4g, 2r, 6r, 3t, 4t, 5t a0, a1, a input- synchronous synchronous address inputs : the address register is triggered by a combination of the rising edge of clk, adv/ld low, cen low and true chip enables. a0 and a1 are ... |
| Description |
256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
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| File Size |
549.84K /
31 Page |
View
it Online |
Download Datasheet |
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